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Implement support for ZA in signal handling in a very similar way to how we implement support for SVE registers, using a signal context structure with optional register state after it. Where present this register state stores the ZA matrix as a series of horizontal vectors numbered from 0 to VL/8 in the endinanness independent format used for vectors. As with SVE we do not allow changes in the vector length during signal return but we do allow ZA to be enabled or disabled. Signed-off-by: Mark Brown <broonie@kernel.org> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Link: https://lore.kernel.org/r/20220419112247.711548-20-broonie@kernel.org Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
304 lines
10 KiB
C
304 lines
10 KiB
C
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
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/*
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* Copyright (C) 2012 ARM Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef _UAPI__ASM_SIGCONTEXT_H
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#define _UAPI__ASM_SIGCONTEXT_H
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#ifndef __ASSEMBLY__
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#include <linux/types.h>
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/*
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* Signal context structure - contains all info to do with the state
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* before the signal handler was invoked.
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*/
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struct sigcontext {
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__u64 fault_address;
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/* AArch64 registers */
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__u64 regs[31];
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__u64 sp;
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__u64 pc;
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__u64 pstate;
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/* 4K reserved for FP/SIMD state and future expansion */
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__u8 __reserved[4096] __attribute__((__aligned__(16)));
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};
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/*
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* Allocation of __reserved[]:
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* (Note: records do not necessarily occur in the order shown here.)
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*
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* size description
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*
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* 0x210 fpsimd_context
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* 0x10 esr_context
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* 0x8a0 sve_context (vl <= 64) (optional)
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* 0x20 extra_context (optional)
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* 0x10 terminator (null _aarch64_ctx)
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*
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* 0x510 (reserved for future allocation)
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*
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* New records that can exceed this space need to be opt-in for userspace, so
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* that an expanded signal frame is not generated unexpectedly. The mechanism
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* for opting in will depend on the extension that generates each new record.
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* The above table documents the maximum set and sizes of records than can be
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* generated when userspace does not opt in for any such extension.
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*/
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/*
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* Header to be used at the beginning of structures extending the user
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* context. Such structures must be placed after the rt_sigframe on the stack
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* and be 16-byte aligned. The last structure must be a dummy one with the
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* magic and size set to 0.
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*/
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struct _aarch64_ctx {
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__u32 magic;
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__u32 size;
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};
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#define FPSIMD_MAGIC 0x46508001
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struct fpsimd_context {
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struct _aarch64_ctx head;
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__u32 fpsr;
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__u32 fpcr;
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__uint128_t vregs[32];
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};
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/*
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* Note: similarly to all other integer fields, each V-register is stored in an
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* endianness-dependent format, with the byte at offset i from the start of the
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* in-memory representation of the register value containing
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*
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* bits [(7 + 8 * i) : (8 * i)] of the register on little-endian hosts; or
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* bits [(127 - 8 * i) : (120 - 8 * i)] on big-endian hosts.
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*/
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/* ESR_EL1 context */
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#define ESR_MAGIC 0x45535201
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struct esr_context {
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struct _aarch64_ctx head;
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__u64 esr;
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};
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/*
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* extra_context: describes extra space in the signal frame for
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* additional structures that don't fit in sigcontext.__reserved[].
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*
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* Note:
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*
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* 1) fpsimd_context, esr_context and extra_context must be placed in
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* sigcontext.__reserved[] if present. They cannot be placed in the
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* extra space. Any other record can be placed either in the extra
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* space or in sigcontext.__reserved[], unless otherwise specified in
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* this file.
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*
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* 2) There must not be more than one extra_context.
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*
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* 3) If extra_context is present, it must be followed immediately in
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* sigcontext.__reserved[] by the terminating null _aarch64_ctx.
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*
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* 4) The extra space to which datap points must start at the first
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* 16-byte aligned address immediately after the terminating null
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* _aarch64_ctx that follows the extra_context structure in
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* __reserved[]. The extra space may overrun the end of __reserved[],
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* as indicated by a sufficiently large value for the size field.
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*
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* 5) The extra space must itself be terminated with a null
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* _aarch64_ctx.
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*/
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#define EXTRA_MAGIC 0x45585401
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struct extra_context {
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struct _aarch64_ctx head;
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__u64 datap; /* 16-byte aligned pointer to extra space cast to __u64 */
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__u32 size; /* size in bytes of the extra space */
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__u32 __reserved[3];
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};
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#define SVE_MAGIC 0x53564501
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struct sve_context {
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struct _aarch64_ctx head;
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__u16 vl;
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__u16 flags;
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__u16 __reserved[2];
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};
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#define SVE_SIG_FLAG_SM 0x1 /* Context describes streaming mode */
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#define ZA_MAGIC 0x54366345
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struct za_context {
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struct _aarch64_ctx head;
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__u16 vl;
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__u16 __reserved[3];
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};
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#endif /* !__ASSEMBLY__ */
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#include <asm/sve_context.h>
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/*
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* The SVE architecture leaves space for future expansion of the
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* vector length beyond its initial architectural limit of 2048 bits
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* (16 quadwords).
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*
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* See linux/Documentation/arm64/sve.rst for a description of the VL/VQ
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* terminology.
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*/
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#define SVE_VQ_BYTES __SVE_VQ_BYTES /* bytes per quadword */
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#define SVE_VQ_MIN __SVE_VQ_MIN
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#define SVE_VQ_MAX __SVE_VQ_MAX
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#define SVE_VL_MIN __SVE_VL_MIN
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#define SVE_VL_MAX __SVE_VL_MAX
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#define SVE_NUM_ZREGS __SVE_NUM_ZREGS
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#define SVE_NUM_PREGS __SVE_NUM_PREGS
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#define sve_vl_valid(vl) __sve_vl_valid(vl)
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#define sve_vq_from_vl(vl) __sve_vq_from_vl(vl)
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#define sve_vl_from_vq(vq) __sve_vl_from_vq(vq)
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/*
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* If the SVE registers are currently live for the thread at signal delivery,
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* sve_context.head.size >=
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* SVE_SIG_CONTEXT_SIZE(sve_vq_from_vl(sve_context.vl))
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* and the register data may be accessed using the SVE_SIG_*() macros.
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*
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* If sve_context.head.size <
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* SVE_SIG_CONTEXT_SIZE(sve_vq_from_vl(sve_context.vl)),
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* the SVE registers were not live for the thread and no register data
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* is included: in this case, the SVE_SIG_*() macros should not be
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* used except for this check.
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*
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* The same convention applies when returning from a signal: a caller
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* will need to remove or resize the sve_context block if it wants to
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* make the SVE registers live when they were previously non-live or
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* vice-versa. This may require the caller to allocate fresh
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* memory and/or move other context blocks in the signal frame.
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*
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* Changing the vector length during signal return is not permitted:
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* sve_context.vl must equal the thread's current vector length when
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* doing a sigreturn.
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*
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* On systems with support for SME the SVE register state may reflect either
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* streaming or non-streaming mode. In streaming mode the streaming mode
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* vector length will be used and the flag SVE_SIG_FLAG_SM will be set in
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* the flags field. It is permitted to enter or leave streaming mode in
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* a signal return, applications should take care to ensure that any difference
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* in vector length between the two modes is handled, including any resizing
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* and movement of context blocks.
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*
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* Note: for all these macros, the "vq" argument denotes the vector length
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* in quadwords (i.e., units of 128 bits).
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*
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* The correct way to obtain vq is to use sve_vq_from_vl(vl). The
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* result is valid if and only if sve_vl_valid(vl) is true. This is
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* guaranteed for a struct sve_context written by the kernel.
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*
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*
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* Additional macros describe the contents and layout of the payload.
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* For each, SVE_SIG_x_OFFSET(args) is the start offset relative to
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* the start of struct sve_context, and SVE_SIG_x_SIZE(args) is the
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* size in bytes:
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*
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* x type description
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* - ---- -----------
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* REGS the entire SVE context
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*
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* ZREGS __uint128_t[SVE_NUM_ZREGS][vq] all Z-registers
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* ZREG __uint128_t[vq] individual Z-register Zn
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*
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* PREGS uint16_t[SVE_NUM_PREGS][vq] all P-registers
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* PREG uint16_t[vq] individual P-register Pn
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*
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* FFR uint16_t[vq] first-fault status register
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*
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* Additional data might be appended in the future.
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*
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* Unlike vregs[] in fpsimd_context, each SVE scalable register (Z-, P- or FFR)
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* is encoded in memory in an endianness-invariant format, with the byte at
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* offset i from the start of the in-memory representation containing bits
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* [(7 + 8 * i) : (8 * i)] of the register value.
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*/
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#define SVE_SIG_ZREG_SIZE(vq) __SVE_ZREG_SIZE(vq)
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#define SVE_SIG_PREG_SIZE(vq) __SVE_PREG_SIZE(vq)
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#define SVE_SIG_FFR_SIZE(vq) __SVE_FFR_SIZE(vq)
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#define SVE_SIG_REGS_OFFSET \
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((sizeof(struct sve_context) + (__SVE_VQ_BYTES - 1)) \
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/ __SVE_VQ_BYTES * __SVE_VQ_BYTES)
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#define SVE_SIG_ZREGS_OFFSET \
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(SVE_SIG_REGS_OFFSET + __SVE_ZREGS_OFFSET)
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#define SVE_SIG_ZREG_OFFSET(vq, n) \
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(SVE_SIG_REGS_OFFSET + __SVE_ZREG_OFFSET(vq, n))
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#define SVE_SIG_ZREGS_SIZE(vq) __SVE_ZREGS_SIZE(vq)
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#define SVE_SIG_PREGS_OFFSET(vq) \
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(SVE_SIG_REGS_OFFSET + __SVE_PREGS_OFFSET(vq))
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#define SVE_SIG_PREG_OFFSET(vq, n) \
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(SVE_SIG_REGS_OFFSET + __SVE_PREG_OFFSET(vq, n))
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#define SVE_SIG_PREGS_SIZE(vq) __SVE_PREGS_SIZE(vq)
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#define SVE_SIG_FFR_OFFSET(vq) \
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(SVE_SIG_REGS_OFFSET + __SVE_FFR_OFFSET(vq))
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#define SVE_SIG_REGS_SIZE(vq) \
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(__SVE_FFR_OFFSET(vq) + __SVE_FFR_SIZE(vq))
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#define SVE_SIG_CONTEXT_SIZE(vq) \
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(SVE_SIG_REGS_OFFSET + SVE_SIG_REGS_SIZE(vq))
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/*
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* If the ZA register is enabled for the thread at signal delivery then,
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* za_context.head.size >= ZA_SIG_CONTEXT_SIZE(sve_vq_from_vl(za_context.vl))
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* and the register data may be accessed using the ZA_SIG_*() macros.
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*
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* If za_context.head.size < ZA_SIG_CONTEXT_SIZE(sve_vq_from_vl(za_context.vl))
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* then ZA was not enabled and no register data was included in which case
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* ZA register was not enabled for the thread and no register data
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* the ZA_SIG_*() macros should not be used except for this check.
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*
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* The same convention applies when returning from a signal: a caller
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* will need to remove or resize the za_context block if it wants to
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* enable the ZA register when it was previously non-live or vice-versa.
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* This may require the caller to allocate fresh memory and/or move other
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* context blocks in the signal frame.
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*
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* Changing the vector length during signal return is not permitted:
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* za_context.vl must equal the thread's current SME vector length when
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* doing a sigreturn.
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*/
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#define ZA_SIG_REGS_OFFSET \
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((sizeof(struct za_context) + (__SVE_VQ_BYTES - 1)) \
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/ __SVE_VQ_BYTES * __SVE_VQ_BYTES)
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#define ZA_SIG_REGS_SIZE(vq) ((vq * __SVE_VQ_BYTES) * (vq * __SVE_VQ_BYTES))
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#define ZA_SIG_ZAV_OFFSET(vq, n) (ZA_SIG_REGS_OFFSET + \
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(SVE_SIG_ZREG_SIZE(vq) * n))
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#define ZA_SIG_CONTEXT_SIZE(vq) \
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(ZA_SIG_REGS_OFFSET + ZA_SIG_REGS_SIZE(vq))
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#endif /* _UAPI__ASM_SIGCONTEXT_H */
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