Nishanth Menon 10d3b16587 arm64: dts: ti: k3-am642: Fix the L2 cache sets ... [ Upstream commit a27a93bf70 ] A53's L2 cache[1] on AM642[2] is 256KB. A53's L2 is fixed line length of 64 bytes and 16-way set-associative cache structure. 256KB of L2 / 64 (line length) = 4096 ways 4096 ways / 16 = 256 sets Fix the l2 cache-sets. [1] https://developer.arm.com/documentation/ddi0500/j/Level-2-Memory-System/About-the-L2-memory-system?lang=en [2] https://www.ti.com/lit/pdf/spruim2 Fixes: 8abae9389b ("arm64: dts: ti: Add support for AM642 SoC") Reported-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20211113043635.4296-1-nm@ti.com Signed-off-by: Sasha Levin <sashal@kernel.org>		2022-01-27 11:03:24 +01:00
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dts	arm64: dts: ti: k3-am642: Fix the L2 cache sets	2022-01-27 11:03:24 +01:00
.gitignore	.gitignore: add SPDX License Identifier	2020-03-25 11:50:48 +01:00
install.sh
Makefile	arm64: move the (z)install rules to arch/arm64/Makefile	2021-08-03 16:19:03 +01:00