Thierry Reding 103afc8e9e pinctrl: tegra: Renumber the GG.0 and GG.1 pins ... There is no need to define these at a specific offset since they are the only pins defined for this SoC generation. Begin numbering them at 0. Signed-off-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20200319122737.3063291-9-thierry.reding@gmail.com Tested-by: Vidya Sagar <vidyas@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>		2020-03-27 11:44:59 +01:00
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Kconfig	This is the bulk of pin control changes for the v5.3 kernel	2019-07-13 15:02:27 -07:00
Makefile	pinctrl: tegra: Add Tegra194 pinmux driver	2019-06-01 19:23:06 +02:00
pinctrl-tegra20.c	This is the bulk of pin control changes for the v5.3 kernel	2019-07-13 15:02:27 -07:00
pinctrl-tegra30.c	This is the bulk of pin control changes for the v5.3 kernel	2019-07-13 15:02:27 -07:00
pinctrl-tegra114.c	This is the bulk of pin control changes for the v5.3 kernel	2019-07-13 15:02:27 -07:00
pinctrl-tegra124.c	This is the bulk of pin control changes for the v5.3 kernel	2019-07-13 15:02:27 -07:00
pinctrl-tegra194.c	pinctrl: tegra: Renumber the GG.0 and GG.1 pins	2020-03-27 11:44:59 +01:00
pinctrl-tegra210.c	pinctrl: tegra210: Add Tegra210 pinctrl pm ops	2019-08-05 11:21:28 +02:00
pinctrl-tegra-xusb.c	pinctrl: use devm_platform_ioremap_resource() to simplify code	2019-11-05 15:33:40 +01:00
pinctrl-tegra.c	pinctrl: tegra: Do not add default pin range on Tegra194	2020-03-27 11:44:30 +01:00
pinctrl-tegra.h	pinctrl: tegra: Fix "Scmitt" -> "Schmitt" typo	2020-03-27 11:41:38 +01:00