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0fbc47d9e4
Adding properties for various register fields in the DT doesn't scale and this information should be in the driver instead. Before this patch these registers (description below) were specified in the DT, every register node contained 3 sections: offset, enable bit, write mask bit. - rockchip,typec-conn-dir : the register of type-c connector direction, for type-c phy0, it must be <0xe580 0 16>; for type-c phy1, it must be <0xe58c 0 16>; - rockchip,usb3tousb2-en : the register of type-c force usb3 to usb2 enable control. for type-c phy0, it must be <0xe580 3 19>; for type-c phy1, it must be <0xe58c 3 19>; - rockchip,external-psm : the register of type-c phy external psm clock selection. for type-c phy0, it must be <0xe588 14 30>; for type-c phy1, it must be <0xe594 14 30>; - rockchip,pipe-status : the register of type-c phy pipe status. for type-c phy0, it must be <0xe5c0 0 0>; for type-c phy1, it must be <0xe5c0 16 16>; After this patch these register definitions are in the driver. So can be removed from the DT. Note that there are 2 type-c phys for RK3399 with different offsets, the driver checks the phy base address of the running instance and applies the right offsets. Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> |
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| allwinner | ||
| amlogic | ||
| broadcom | ||
| hisilicon | ||
| lantiq | ||
| marvell | ||
| mediatek | ||
| motorola | ||
| qualcomm | ||
| ralink | ||
| renesas | ||
| rockchip | ||
| samsung | ||
| st | ||
| tegra | ||
| ti | ||
| Kconfig | ||
| Makefile | ||
| phy-core.c | ||
| phy-lpc18xx-usb-otg.c | ||
| phy-pistachio-usb.c | ||
| phy-xgene.c | ||