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2d471b20c5
Rather than have separate opaque setter functions that are easy to overlook and lead to repetitive boilerplate in drivers, let's pass the relevant initialisation parameters directly to iommu_device_register(). Acked-by: Will Deacon <will@kernel.org> Signed-off-by: Robin Murphy <robin.murphy@arm.com> Link: https://lore.kernel.org/r/ab001b87c533b6f4db71eb90db6f888953986c36.1617285386.git.robin.murphy@arm.com Signed-off-by: Joerg Roedel <jroedel@suse.de>
1082 lines
31 KiB
C
1082 lines
31 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2015-2016 MediaTek Inc.
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* Author: Yong Wu <yong.wu@mediatek.com>
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*/
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#include <linux/bitfield.h>
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#include <linux/bug.h>
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#include <linux/clk.h>
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#include <linux/component.h>
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#include <linux/device.h>
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#include <linux/dma-direct.h>
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#include <linux/dma-iommu.h>
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#include <linux/err.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/iommu.h>
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#include <linux/iopoll.h>
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#include <linux/list.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/of_address.h>
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#include <linux/of_iommu.h>
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#include <linux/of_irq.h>
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#include <linux/of_platform.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/regmap.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include <linux/soc/mediatek/infracfg.h>
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#include <asm/barrier.h>
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#include <soc/mediatek/smi.h>
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#include "mtk_iommu.h"
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#define REG_MMU_PT_BASE_ADDR 0x000
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#define MMU_PT_ADDR_MASK GENMASK(31, 7)
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#define REG_MMU_INVALIDATE 0x020
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#define F_ALL_INVLD 0x2
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#define F_MMU_INV_RANGE 0x1
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#define REG_MMU_INVLD_START_A 0x024
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#define REG_MMU_INVLD_END_A 0x028
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#define REG_MMU_INV_SEL_GEN2 0x02c
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#define REG_MMU_INV_SEL_GEN1 0x038
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#define F_INVLD_EN0 BIT(0)
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#define F_INVLD_EN1 BIT(1)
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#define REG_MMU_MISC_CTRL 0x048
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#define F_MMU_IN_ORDER_WR_EN_MASK (BIT(1) | BIT(17))
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#define F_MMU_STANDARD_AXI_MODE_MASK (BIT(3) | BIT(19))
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#define REG_MMU_DCM_DIS 0x050
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#define REG_MMU_WR_LEN_CTRL 0x054
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#define F_MMU_WR_THROT_DIS_MASK (BIT(5) | BIT(21))
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#define REG_MMU_CTRL_REG 0x110
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#define F_MMU_TF_PROT_TO_PROGRAM_ADDR (2 << 4)
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#define F_MMU_PREFETCH_RT_REPLACE_MOD BIT(4)
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#define F_MMU_TF_PROT_TO_PROGRAM_ADDR_MT8173 (2 << 5)
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#define REG_MMU_IVRP_PADDR 0x114
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#define REG_MMU_VLD_PA_RNG 0x118
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#define F_MMU_VLD_PA_RNG(EA, SA) (((EA) << 8) | (SA))
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#define REG_MMU_INT_CONTROL0 0x120
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#define F_L2_MULIT_HIT_EN BIT(0)
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#define F_TABLE_WALK_FAULT_INT_EN BIT(1)
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#define F_PREETCH_FIFO_OVERFLOW_INT_EN BIT(2)
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#define F_MISS_FIFO_OVERFLOW_INT_EN BIT(3)
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#define F_PREFETCH_FIFO_ERR_INT_EN BIT(5)
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#define F_MISS_FIFO_ERR_INT_EN BIT(6)
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#define F_INT_CLR_BIT BIT(12)
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#define REG_MMU_INT_MAIN_CONTROL 0x124
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/* mmu0 | mmu1 */
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#define F_INT_TRANSLATION_FAULT (BIT(0) | BIT(7))
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#define F_INT_MAIN_MULTI_HIT_FAULT (BIT(1) | BIT(8))
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#define F_INT_INVALID_PA_FAULT (BIT(2) | BIT(9))
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#define F_INT_ENTRY_REPLACEMENT_FAULT (BIT(3) | BIT(10))
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#define F_INT_TLB_MISS_FAULT (BIT(4) | BIT(11))
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#define F_INT_MISS_TRANSACTION_FIFO_FAULT (BIT(5) | BIT(12))
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#define F_INT_PRETETCH_TRANSATION_FIFO_FAULT (BIT(6) | BIT(13))
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#define REG_MMU_CPE_DONE 0x12C
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#define REG_MMU_FAULT_ST1 0x134
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#define F_REG_MMU0_FAULT_MASK GENMASK(6, 0)
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#define F_REG_MMU1_FAULT_MASK GENMASK(13, 7)
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#define REG_MMU0_FAULT_VA 0x13c
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#define F_MMU_INVAL_VA_31_12_MASK GENMASK(31, 12)
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#define F_MMU_INVAL_VA_34_32_MASK GENMASK(11, 9)
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#define F_MMU_INVAL_PA_34_32_MASK GENMASK(8, 6)
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#define F_MMU_FAULT_VA_WRITE_BIT BIT(1)
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#define F_MMU_FAULT_VA_LAYER_BIT BIT(0)
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#define REG_MMU0_INVLD_PA 0x140
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#define REG_MMU1_FAULT_VA 0x144
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#define REG_MMU1_INVLD_PA 0x148
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#define REG_MMU0_INT_ID 0x150
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#define REG_MMU1_INT_ID 0x154
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#define F_MMU_INT_ID_COMM_ID(a) (((a) >> 9) & 0x7)
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#define F_MMU_INT_ID_SUB_COMM_ID(a) (((a) >> 7) & 0x3)
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#define F_MMU_INT_ID_LARB_ID(a) (((a) >> 7) & 0x7)
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#define F_MMU_INT_ID_PORT_ID(a) (((a) >> 2) & 0x1f)
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#define MTK_PROTECT_PA_ALIGN 256
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#define HAS_4GB_MODE BIT(0)
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/* HW will use the EMI clock if there isn't the "bclk". */
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#define HAS_BCLK BIT(1)
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#define HAS_VLD_PA_RNG BIT(2)
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#define RESET_AXI BIT(3)
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#define OUT_ORDER_WR_EN BIT(4)
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#define HAS_SUB_COMM BIT(5)
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#define WR_THROT_EN BIT(6)
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#define HAS_LEGACY_IVRP_PADDR BIT(7)
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#define IOVA_34_EN BIT(8)
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#define MTK_IOMMU_HAS_FLAG(pdata, _x) \
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((((pdata)->flags) & (_x)) == (_x))
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struct mtk_iommu_domain {
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struct io_pgtable_cfg cfg;
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struct io_pgtable_ops *iop;
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struct mtk_iommu_data *data;
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struct iommu_domain domain;
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};
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static const struct iommu_ops mtk_iommu_ops;
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static int mtk_iommu_hw_init(const struct mtk_iommu_data *data);
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#define MTK_IOMMU_TLB_ADDR(iova) ({ \
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dma_addr_t _addr = iova; \
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((lower_32_bits(_addr) & GENMASK(31, 12)) | upper_32_bits(_addr));\
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})
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/*
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* In M4U 4GB mode, the physical address is remapped as below:
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*
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* CPU Physical address:
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* ====================
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*
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* 0 1G 2G 3G 4G 5G
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* |---A---|---B---|---C---|---D---|---E---|
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* +--I/O--+------------Memory-------------+
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*
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* IOMMU output physical address:
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* =============================
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*
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* 4G 5G 6G 7G 8G
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* |---E---|---B---|---C---|---D---|
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* +------------Memory-------------+
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*
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* The Region 'A'(I/O) can NOT be mapped by M4U; For Region 'B'/'C'/'D', the
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* bit32 of the CPU physical address always is needed to set, and for Region
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* 'E', the CPU physical address keep as is.
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* Additionally, The iommu consumers always use the CPU phyiscal address.
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*/
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#define MTK_IOMMU_4GB_MODE_REMAP_BASE 0x140000000UL
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static LIST_HEAD(m4ulist); /* List all the M4U HWs */
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#define for_each_m4u(data) list_for_each_entry(data, &m4ulist, list)
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struct mtk_iommu_iova_region {
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dma_addr_t iova_base;
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unsigned long long size;
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};
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static const struct mtk_iommu_iova_region single_domain[] = {
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{.iova_base = 0, .size = SZ_4G},
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};
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static const struct mtk_iommu_iova_region mt8192_multi_dom[] = {
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{ .iova_base = 0x0, .size = SZ_4G}, /* disp: 0 ~ 4G */
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#if IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT)
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{ .iova_base = SZ_4G, .size = SZ_4G}, /* vdec: 4G ~ 8G */
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{ .iova_base = SZ_4G * 2, .size = SZ_4G}, /* CAM/MDP: 8G ~ 12G */
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{ .iova_base = 0x240000000ULL, .size = 0x4000000}, /* CCU0 */
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{ .iova_base = 0x244000000ULL, .size = 0x4000000}, /* CCU1 */
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#endif
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};
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/*
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* There may be 1 or 2 M4U HWs, But we always expect they are in the same domain
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* for the performance.
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*
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* Here always return the mtk_iommu_data of the first probed M4U where the
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* iommu domain information is recorded.
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*/
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static struct mtk_iommu_data *mtk_iommu_get_m4u_data(void)
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{
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struct mtk_iommu_data *data;
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for_each_m4u(data)
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return data;
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return NULL;
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}
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static struct mtk_iommu_domain *to_mtk_domain(struct iommu_domain *dom)
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{
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return container_of(dom, struct mtk_iommu_domain, domain);
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}
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static void mtk_iommu_tlb_flush_all(struct mtk_iommu_data *data)
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{
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for_each_m4u(data) {
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if (pm_runtime_get_if_in_use(data->dev) <= 0)
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continue;
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writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0,
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data->base + data->plat_data->inv_sel_reg);
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writel_relaxed(F_ALL_INVLD, data->base + REG_MMU_INVALIDATE);
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wmb(); /* Make sure the tlb flush all done */
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pm_runtime_put(data->dev);
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}
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}
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static void mtk_iommu_tlb_flush_range_sync(unsigned long iova, size_t size,
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size_t granule,
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struct mtk_iommu_data *data)
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{
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bool has_pm = !!data->dev->pm_domain;
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unsigned long flags;
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int ret;
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u32 tmp;
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for_each_m4u(data) {
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if (has_pm) {
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if (pm_runtime_get_if_in_use(data->dev) <= 0)
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continue;
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}
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spin_lock_irqsave(&data->tlb_lock, flags);
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writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0,
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data->base + data->plat_data->inv_sel_reg);
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writel_relaxed(MTK_IOMMU_TLB_ADDR(iova),
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data->base + REG_MMU_INVLD_START_A);
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writel_relaxed(MTK_IOMMU_TLB_ADDR(iova + size - 1),
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data->base + REG_MMU_INVLD_END_A);
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writel_relaxed(F_MMU_INV_RANGE,
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data->base + REG_MMU_INVALIDATE);
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/* tlb sync */
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ret = readl_poll_timeout_atomic(data->base + REG_MMU_CPE_DONE,
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tmp, tmp != 0, 10, 1000);
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if (ret) {
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dev_warn(data->dev,
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"Partial TLB flush timed out, falling back to full flush\n");
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mtk_iommu_tlb_flush_all(data);
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}
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/* Clear the CPE status */
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writel_relaxed(0, data->base + REG_MMU_CPE_DONE);
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spin_unlock_irqrestore(&data->tlb_lock, flags);
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if (has_pm)
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pm_runtime_put(data->dev);
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}
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}
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static irqreturn_t mtk_iommu_isr(int irq, void *dev_id)
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{
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struct mtk_iommu_data *data = dev_id;
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struct mtk_iommu_domain *dom = data->m4u_dom;
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unsigned int fault_larb, fault_port, sub_comm = 0;
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u32 int_state, regval, va34_32, pa34_32;
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u64 fault_iova, fault_pa;
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bool layer, write;
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/* Read error info from registers */
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int_state = readl_relaxed(data->base + REG_MMU_FAULT_ST1);
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if (int_state & F_REG_MMU0_FAULT_MASK) {
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regval = readl_relaxed(data->base + REG_MMU0_INT_ID);
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fault_iova = readl_relaxed(data->base + REG_MMU0_FAULT_VA);
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fault_pa = readl_relaxed(data->base + REG_MMU0_INVLD_PA);
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} else {
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regval = readl_relaxed(data->base + REG_MMU1_INT_ID);
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fault_iova = readl_relaxed(data->base + REG_MMU1_FAULT_VA);
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fault_pa = readl_relaxed(data->base + REG_MMU1_INVLD_PA);
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}
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layer = fault_iova & F_MMU_FAULT_VA_LAYER_BIT;
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write = fault_iova & F_MMU_FAULT_VA_WRITE_BIT;
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if (MTK_IOMMU_HAS_FLAG(data->plat_data, IOVA_34_EN)) {
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va34_32 = FIELD_GET(F_MMU_INVAL_VA_34_32_MASK, fault_iova);
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pa34_32 = FIELD_GET(F_MMU_INVAL_PA_34_32_MASK, fault_iova);
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fault_iova = fault_iova & F_MMU_INVAL_VA_31_12_MASK;
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fault_iova |= (u64)va34_32 << 32;
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fault_pa |= (u64)pa34_32 << 32;
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}
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fault_port = F_MMU_INT_ID_PORT_ID(regval);
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if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_SUB_COMM)) {
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fault_larb = F_MMU_INT_ID_COMM_ID(regval);
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sub_comm = F_MMU_INT_ID_SUB_COMM_ID(regval);
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} else {
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fault_larb = F_MMU_INT_ID_LARB_ID(regval);
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}
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fault_larb = data->plat_data->larbid_remap[fault_larb][sub_comm];
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if (report_iommu_fault(&dom->domain, data->dev, fault_iova,
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write ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ)) {
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dev_err_ratelimited(
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data->dev,
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"fault type=0x%x iova=0x%llx pa=0x%llx larb=%d port=%d layer=%d %s\n",
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int_state, fault_iova, fault_pa, fault_larb, fault_port,
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layer, write ? "write" : "read");
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}
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/* Interrupt clear */
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regval = readl_relaxed(data->base + REG_MMU_INT_CONTROL0);
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regval |= F_INT_CLR_BIT;
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writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL0);
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mtk_iommu_tlb_flush_all(data);
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return IRQ_HANDLED;
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}
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static int mtk_iommu_get_domain_id(struct device *dev,
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const struct mtk_iommu_plat_data *plat_data)
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{
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const struct mtk_iommu_iova_region *rgn = plat_data->iova_region;
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const struct bus_dma_region *dma_rgn = dev->dma_range_map;
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int i, candidate = -1;
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dma_addr_t dma_end;
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if (!dma_rgn || plat_data->iova_region_nr == 1)
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return 0;
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dma_end = dma_rgn->dma_start + dma_rgn->size - 1;
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for (i = 0; i < plat_data->iova_region_nr; i++, rgn++) {
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/* Best fit. */
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if (dma_rgn->dma_start == rgn->iova_base &&
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dma_end == rgn->iova_base + rgn->size - 1)
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return i;
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/* ok if it is inside this region. */
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if (dma_rgn->dma_start >= rgn->iova_base &&
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dma_end < rgn->iova_base + rgn->size)
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candidate = i;
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}
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if (candidate >= 0)
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return candidate;
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dev_err(dev, "Can NOT find the iommu domain id(%pad 0x%llx).\n",
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&dma_rgn->dma_start, dma_rgn->size);
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return -EINVAL;
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}
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static void mtk_iommu_config(struct mtk_iommu_data *data, struct device *dev,
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bool enable, unsigned int domid)
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{
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struct mtk_smi_larb_iommu *larb_mmu;
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unsigned int larbid, portid;
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struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
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const struct mtk_iommu_iova_region *region;
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int i;
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for (i = 0; i < fwspec->num_ids; ++i) {
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larbid = MTK_M4U_TO_LARB(fwspec->ids[i]);
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portid = MTK_M4U_TO_PORT(fwspec->ids[i]);
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larb_mmu = &data->larb_imu[larbid];
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region = data->plat_data->iova_region + domid;
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larb_mmu->bank[portid] = upper_32_bits(region->iova_base);
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dev_dbg(dev, "%s iommu for larb(%s) port %d dom %d bank %d.\n",
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enable ? "enable" : "disable", dev_name(larb_mmu->dev),
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portid, domid, larb_mmu->bank[portid]);
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if (enable)
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larb_mmu->mmu |= MTK_SMI_MMU_EN(portid);
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else
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larb_mmu->mmu &= ~MTK_SMI_MMU_EN(portid);
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}
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}
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static int mtk_iommu_domain_finalise(struct mtk_iommu_domain *dom,
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struct mtk_iommu_data *data,
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unsigned int domid)
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{
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const struct mtk_iommu_iova_region *region;
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/* Use the exist domain as there is only one pgtable here. */
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if (data->m4u_dom) {
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dom->iop = data->m4u_dom->iop;
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dom->cfg = data->m4u_dom->cfg;
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dom->domain.pgsize_bitmap = data->m4u_dom->cfg.pgsize_bitmap;
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goto update_iova_region;
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}
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dom->cfg = (struct io_pgtable_cfg) {
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.quirks = IO_PGTABLE_QUIRK_ARM_NS |
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IO_PGTABLE_QUIRK_NO_PERMS |
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IO_PGTABLE_QUIRK_ARM_MTK_EXT,
|
|
.pgsize_bitmap = mtk_iommu_ops.pgsize_bitmap,
|
|
.ias = MTK_IOMMU_HAS_FLAG(data->plat_data, IOVA_34_EN) ? 34 : 32,
|
|
.iommu_dev = data->dev,
|
|
};
|
|
|
|
if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_4GB_MODE))
|
|
dom->cfg.oas = data->enable_4GB ? 33 : 32;
|
|
else
|
|
dom->cfg.oas = 35;
|
|
|
|
dom->iop = alloc_io_pgtable_ops(ARM_V7S, &dom->cfg, data);
|
|
if (!dom->iop) {
|
|
dev_err(data->dev, "Failed to alloc io pgtable\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
/* Update our support page sizes bitmap */
|
|
dom->domain.pgsize_bitmap = dom->cfg.pgsize_bitmap;
|
|
|
|
update_iova_region:
|
|
/* Update the iova region for this domain */
|
|
region = data->plat_data->iova_region + domid;
|
|
dom->domain.geometry.aperture_start = region->iova_base;
|
|
dom->domain.geometry.aperture_end = region->iova_base + region->size - 1;
|
|
dom->domain.geometry.force_aperture = true;
|
|
return 0;
|
|
}
|
|
|
|
static struct iommu_domain *mtk_iommu_domain_alloc(unsigned type)
|
|
{
|
|
struct mtk_iommu_domain *dom;
|
|
|
|
if (type != IOMMU_DOMAIN_DMA)
|
|
return NULL;
|
|
|
|
dom = kzalloc(sizeof(*dom), GFP_KERNEL);
|
|
if (!dom)
|
|
return NULL;
|
|
|
|
if (iommu_get_dma_cookie(&dom->domain)) {
|
|
kfree(dom);
|
|
return NULL;
|
|
}
|
|
|
|
return &dom->domain;
|
|
}
|
|
|
|
static void mtk_iommu_domain_free(struct iommu_domain *domain)
|
|
{
|
|
iommu_put_dma_cookie(domain);
|
|
kfree(to_mtk_domain(domain));
|
|
}
|
|
|
|
static int mtk_iommu_attach_device(struct iommu_domain *domain,
|
|
struct device *dev)
|
|
{
|
|
struct mtk_iommu_data *data = dev_iommu_priv_get(dev);
|
|
struct mtk_iommu_domain *dom = to_mtk_domain(domain);
|
|
struct device *m4udev = data->dev;
|
|
int ret, domid;
|
|
|
|
domid = mtk_iommu_get_domain_id(dev, data->plat_data);
|
|
if (domid < 0)
|
|
return domid;
|
|
|
|
if (!dom->data) {
|
|
if (mtk_iommu_domain_finalise(dom, data, domid))
|
|
return -ENODEV;
|
|
dom->data = data;
|
|
}
|
|
|
|
if (!data->m4u_dom) { /* Initialize the M4U HW */
|
|
ret = pm_runtime_resume_and_get(m4udev);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
ret = mtk_iommu_hw_init(data);
|
|
if (ret) {
|
|
pm_runtime_put(m4udev);
|
|
return ret;
|
|
}
|
|
data->m4u_dom = dom;
|
|
writel(dom->cfg.arm_v7s_cfg.ttbr & MMU_PT_ADDR_MASK,
|
|
data->base + REG_MMU_PT_BASE_ADDR);
|
|
|
|
pm_runtime_put(m4udev);
|
|
}
|
|
|
|
mtk_iommu_config(data, dev, true, domid);
|
|
return 0;
|
|
}
|
|
|
|
static void mtk_iommu_detach_device(struct iommu_domain *domain,
|
|
struct device *dev)
|
|
{
|
|
struct mtk_iommu_data *data = dev_iommu_priv_get(dev);
|
|
|
|
mtk_iommu_config(data, dev, false, 0);
|
|
}
|
|
|
|
static int mtk_iommu_map(struct iommu_domain *domain, unsigned long iova,
|
|
phys_addr_t paddr, size_t size, int prot, gfp_t gfp)
|
|
{
|
|
struct mtk_iommu_domain *dom = to_mtk_domain(domain);
|
|
|
|
/* The "4GB mode" M4U physically can not use the lower remap of Dram. */
|
|
if (dom->data->enable_4GB)
|
|
paddr |= BIT_ULL(32);
|
|
|
|
/* Synchronize with the tlb_lock */
|
|
return dom->iop->map(dom->iop, iova, paddr, size, prot, gfp);
|
|
}
|
|
|
|
static size_t mtk_iommu_unmap(struct iommu_domain *domain,
|
|
unsigned long iova, size_t size,
|
|
struct iommu_iotlb_gather *gather)
|
|
{
|
|
struct mtk_iommu_domain *dom = to_mtk_domain(domain);
|
|
unsigned long end = iova + size - 1;
|
|
|
|
if (gather->start > iova)
|
|
gather->start = iova;
|
|
if (gather->end < end)
|
|
gather->end = end;
|
|
return dom->iop->unmap(dom->iop, iova, size, gather);
|
|
}
|
|
|
|
static void mtk_iommu_flush_iotlb_all(struct iommu_domain *domain)
|
|
{
|
|
struct mtk_iommu_domain *dom = to_mtk_domain(domain);
|
|
|
|
mtk_iommu_tlb_flush_all(dom->data);
|
|
}
|
|
|
|
static void mtk_iommu_iotlb_sync(struct iommu_domain *domain,
|
|
struct iommu_iotlb_gather *gather)
|
|
{
|
|
struct mtk_iommu_domain *dom = to_mtk_domain(domain);
|
|
size_t length = gather->end - gather->start + 1;
|
|
|
|
mtk_iommu_tlb_flush_range_sync(gather->start, length, gather->pgsize,
|
|
dom->data);
|
|
}
|
|
|
|
static void mtk_iommu_sync_map(struct iommu_domain *domain, unsigned long iova,
|
|
size_t size)
|
|
{
|
|
struct mtk_iommu_domain *dom = to_mtk_domain(domain);
|
|
|
|
mtk_iommu_tlb_flush_range_sync(iova, size, size, dom->data);
|
|
}
|
|
|
|
static phys_addr_t mtk_iommu_iova_to_phys(struct iommu_domain *domain,
|
|
dma_addr_t iova)
|
|
{
|
|
struct mtk_iommu_domain *dom = to_mtk_domain(domain);
|
|
phys_addr_t pa;
|
|
|
|
pa = dom->iop->iova_to_phys(dom->iop, iova);
|
|
if (dom->data->enable_4GB && pa >= MTK_IOMMU_4GB_MODE_REMAP_BASE)
|
|
pa &= ~BIT_ULL(32);
|
|
|
|
return pa;
|
|
}
|
|
|
|
static struct iommu_device *mtk_iommu_probe_device(struct device *dev)
|
|
{
|
|
struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
|
|
struct mtk_iommu_data *data;
|
|
|
|
if (!fwspec || fwspec->ops != &mtk_iommu_ops)
|
|
return ERR_PTR(-ENODEV); /* Not a iommu client device */
|
|
|
|
data = dev_iommu_priv_get(dev);
|
|
|
|
return &data->iommu;
|
|
}
|
|
|
|
static void mtk_iommu_release_device(struct device *dev)
|
|
{
|
|
struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
|
|
|
|
if (!fwspec || fwspec->ops != &mtk_iommu_ops)
|
|
return;
|
|
|
|
iommu_fwspec_free(dev);
|
|
}
|
|
|
|
static struct iommu_group *mtk_iommu_device_group(struct device *dev)
|
|
{
|
|
struct mtk_iommu_data *data = mtk_iommu_get_m4u_data();
|
|
struct iommu_group *group;
|
|
int domid;
|
|
|
|
if (!data)
|
|
return ERR_PTR(-ENODEV);
|
|
|
|
domid = mtk_iommu_get_domain_id(dev, data->plat_data);
|
|
if (domid < 0)
|
|
return ERR_PTR(domid);
|
|
|
|
group = data->m4u_group[domid];
|
|
if (!group) {
|
|
group = iommu_group_alloc();
|
|
if (!IS_ERR(group))
|
|
data->m4u_group[domid] = group;
|
|
} else {
|
|
iommu_group_ref_get(group);
|
|
}
|
|
return group;
|
|
}
|
|
|
|
static int mtk_iommu_of_xlate(struct device *dev, struct of_phandle_args *args)
|
|
{
|
|
struct platform_device *m4updev;
|
|
|
|
if (args->args_count != 1) {
|
|
dev_err(dev, "invalid #iommu-cells(%d) property for IOMMU\n",
|
|
args->args_count);
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (!dev_iommu_priv_get(dev)) {
|
|
/* Get the m4u device */
|
|
m4updev = of_find_device_by_node(args->np);
|
|
if (WARN_ON(!m4updev))
|
|
return -EINVAL;
|
|
|
|
dev_iommu_priv_set(dev, platform_get_drvdata(m4updev));
|
|
}
|
|
|
|
return iommu_fwspec_add_ids(dev, args->args, 1);
|
|
}
|
|
|
|
static void mtk_iommu_get_resv_regions(struct device *dev,
|
|
struct list_head *head)
|
|
{
|
|
struct mtk_iommu_data *data = dev_iommu_priv_get(dev);
|
|
unsigned int domid = mtk_iommu_get_domain_id(dev, data->plat_data), i;
|
|
const struct mtk_iommu_iova_region *resv, *curdom;
|
|
struct iommu_resv_region *region;
|
|
int prot = IOMMU_WRITE | IOMMU_READ;
|
|
|
|
if ((int)domid < 0)
|
|
return;
|
|
curdom = data->plat_data->iova_region + domid;
|
|
for (i = 0; i < data->plat_data->iova_region_nr; i++) {
|
|
resv = data->plat_data->iova_region + i;
|
|
|
|
/* Only reserve when the region is inside the current domain */
|
|
if (resv->iova_base <= curdom->iova_base ||
|
|
resv->iova_base + resv->size >= curdom->iova_base + curdom->size)
|
|
continue;
|
|
|
|
region = iommu_alloc_resv_region(resv->iova_base, resv->size,
|
|
prot, IOMMU_RESV_RESERVED);
|
|
if (!region)
|
|
return;
|
|
|
|
list_add_tail(®ion->list, head);
|
|
}
|
|
}
|
|
|
|
static const struct iommu_ops mtk_iommu_ops = {
|
|
.domain_alloc = mtk_iommu_domain_alloc,
|
|
.domain_free = mtk_iommu_domain_free,
|
|
.attach_dev = mtk_iommu_attach_device,
|
|
.detach_dev = mtk_iommu_detach_device,
|
|
.map = mtk_iommu_map,
|
|
.unmap = mtk_iommu_unmap,
|
|
.flush_iotlb_all = mtk_iommu_flush_iotlb_all,
|
|
.iotlb_sync = mtk_iommu_iotlb_sync,
|
|
.iotlb_sync_map = mtk_iommu_sync_map,
|
|
.iova_to_phys = mtk_iommu_iova_to_phys,
|
|
.probe_device = mtk_iommu_probe_device,
|
|
.release_device = mtk_iommu_release_device,
|
|
.device_group = mtk_iommu_device_group,
|
|
.of_xlate = mtk_iommu_of_xlate,
|
|
.get_resv_regions = mtk_iommu_get_resv_regions,
|
|
.put_resv_regions = generic_iommu_put_resv_regions,
|
|
.pgsize_bitmap = SZ_4K | SZ_64K | SZ_1M | SZ_16M,
|
|
.owner = THIS_MODULE,
|
|
};
|
|
|
|
static int mtk_iommu_hw_init(const struct mtk_iommu_data *data)
|
|
{
|
|
u32 regval;
|
|
|
|
if (data->plat_data->m4u_plat == M4U_MT8173) {
|
|
regval = F_MMU_PREFETCH_RT_REPLACE_MOD |
|
|
F_MMU_TF_PROT_TO_PROGRAM_ADDR_MT8173;
|
|
} else {
|
|
regval = readl_relaxed(data->base + REG_MMU_CTRL_REG);
|
|
regval |= F_MMU_TF_PROT_TO_PROGRAM_ADDR;
|
|
}
|
|
writel_relaxed(regval, data->base + REG_MMU_CTRL_REG);
|
|
|
|
regval = F_L2_MULIT_HIT_EN |
|
|
F_TABLE_WALK_FAULT_INT_EN |
|
|
F_PREETCH_FIFO_OVERFLOW_INT_EN |
|
|
F_MISS_FIFO_OVERFLOW_INT_EN |
|
|
F_PREFETCH_FIFO_ERR_INT_EN |
|
|
F_MISS_FIFO_ERR_INT_EN;
|
|
writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL0);
|
|
|
|
regval = F_INT_TRANSLATION_FAULT |
|
|
F_INT_MAIN_MULTI_HIT_FAULT |
|
|
F_INT_INVALID_PA_FAULT |
|
|
F_INT_ENTRY_REPLACEMENT_FAULT |
|
|
F_INT_TLB_MISS_FAULT |
|
|
F_INT_MISS_TRANSACTION_FIFO_FAULT |
|
|
F_INT_PRETETCH_TRANSATION_FIFO_FAULT;
|
|
writel_relaxed(regval, data->base + REG_MMU_INT_MAIN_CONTROL);
|
|
|
|
if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_LEGACY_IVRP_PADDR))
|
|
regval = (data->protect_base >> 1) | (data->enable_4GB << 31);
|
|
else
|
|
regval = lower_32_bits(data->protect_base) |
|
|
upper_32_bits(data->protect_base);
|
|
writel_relaxed(regval, data->base + REG_MMU_IVRP_PADDR);
|
|
|
|
if (data->enable_4GB &&
|
|
MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_VLD_PA_RNG)) {
|
|
/*
|
|
* If 4GB mode is enabled, the validate PA range is from
|
|
* 0x1_0000_0000 to 0x1_ffff_ffff. here record bit[32:30].
|
|
*/
|
|
regval = F_MMU_VLD_PA_RNG(7, 4);
|
|
writel_relaxed(regval, data->base + REG_MMU_VLD_PA_RNG);
|
|
}
|
|
writel_relaxed(0, data->base + REG_MMU_DCM_DIS);
|
|
if (MTK_IOMMU_HAS_FLAG(data->plat_data, WR_THROT_EN)) {
|
|
/* write command throttling mode */
|
|
regval = readl_relaxed(data->base + REG_MMU_WR_LEN_CTRL);
|
|
regval &= ~F_MMU_WR_THROT_DIS_MASK;
|
|
writel_relaxed(regval, data->base + REG_MMU_WR_LEN_CTRL);
|
|
}
|
|
|
|
if (MTK_IOMMU_HAS_FLAG(data->plat_data, RESET_AXI)) {
|
|
/* The register is called STANDARD_AXI_MODE in this case */
|
|
regval = 0;
|
|
} else {
|
|
regval = readl_relaxed(data->base + REG_MMU_MISC_CTRL);
|
|
regval &= ~F_MMU_STANDARD_AXI_MODE_MASK;
|
|
if (MTK_IOMMU_HAS_FLAG(data->plat_data, OUT_ORDER_WR_EN))
|
|
regval &= ~F_MMU_IN_ORDER_WR_EN_MASK;
|
|
}
|
|
writel_relaxed(regval, data->base + REG_MMU_MISC_CTRL);
|
|
|
|
if (devm_request_irq(data->dev, data->irq, mtk_iommu_isr, 0,
|
|
dev_name(data->dev), (void *)data)) {
|
|
writel_relaxed(0, data->base + REG_MMU_PT_BASE_ADDR);
|
|
dev_err(data->dev, "Failed @ IRQ-%d Request\n", data->irq);
|
|
return -ENODEV;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct component_master_ops mtk_iommu_com_ops = {
|
|
.bind = mtk_iommu_bind,
|
|
.unbind = mtk_iommu_unbind,
|
|
};
|
|
|
|
static int mtk_iommu_probe(struct platform_device *pdev)
|
|
{
|
|
struct mtk_iommu_data *data;
|
|
struct device *dev = &pdev->dev;
|
|
struct device_node *larbnode, *smicomm_node;
|
|
struct platform_device *plarbdev;
|
|
struct device_link *link;
|
|
struct resource *res;
|
|
resource_size_t ioaddr;
|
|
struct component_match *match = NULL;
|
|
struct regmap *infracfg;
|
|
void *protect;
|
|
int i, larb_nr, ret;
|
|
u32 val;
|
|
char *p;
|
|
|
|
data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
|
|
if (!data)
|
|
return -ENOMEM;
|
|
data->dev = dev;
|
|
data->plat_data = of_device_get_match_data(dev);
|
|
|
|
/* Protect memory. HW will access here while translation fault.*/
|
|
protect = devm_kzalloc(dev, MTK_PROTECT_PA_ALIGN * 2, GFP_KERNEL);
|
|
if (!protect)
|
|
return -ENOMEM;
|
|
data->protect_base = ALIGN(virt_to_phys(protect), MTK_PROTECT_PA_ALIGN);
|
|
|
|
if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_4GB_MODE)) {
|
|
switch (data->plat_data->m4u_plat) {
|
|
case M4U_MT2712:
|
|
p = "mediatek,mt2712-infracfg";
|
|
break;
|
|
case M4U_MT8173:
|
|
p = "mediatek,mt8173-infracfg";
|
|
break;
|
|
default:
|
|
p = NULL;
|
|
}
|
|
|
|
infracfg = syscon_regmap_lookup_by_compatible(p);
|
|
|
|
if (IS_ERR(infracfg))
|
|
return PTR_ERR(infracfg);
|
|
|
|
ret = regmap_read(infracfg, REG_INFRA_MISC, &val);
|
|
if (ret)
|
|
return ret;
|
|
data->enable_4GB = !!(val & F_DDR_4GB_SUPPORT_EN);
|
|
}
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
data->base = devm_ioremap_resource(dev, res);
|
|
if (IS_ERR(data->base))
|
|
return PTR_ERR(data->base);
|
|
ioaddr = res->start;
|
|
|
|
data->irq = platform_get_irq(pdev, 0);
|
|
if (data->irq < 0)
|
|
return data->irq;
|
|
|
|
if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_BCLK)) {
|
|
data->bclk = devm_clk_get(dev, "bclk");
|
|
if (IS_ERR(data->bclk))
|
|
return PTR_ERR(data->bclk);
|
|
}
|
|
|
|
larb_nr = of_count_phandle_with_args(dev->of_node,
|
|
"mediatek,larbs", NULL);
|
|
if (larb_nr < 0)
|
|
return larb_nr;
|
|
|
|
for (i = 0; i < larb_nr; i++) {
|
|
u32 id;
|
|
|
|
larbnode = of_parse_phandle(dev->of_node, "mediatek,larbs", i);
|
|
if (!larbnode)
|
|
return -EINVAL;
|
|
|
|
if (!of_device_is_available(larbnode)) {
|
|
of_node_put(larbnode);
|
|
continue;
|
|
}
|
|
|
|
ret = of_property_read_u32(larbnode, "mediatek,larb-id", &id);
|
|
if (ret)/* The id is consecutive if there is no this property */
|
|
id = i;
|
|
|
|
plarbdev = of_find_device_by_node(larbnode);
|
|
if (!plarbdev) {
|
|
of_node_put(larbnode);
|
|
return -EPROBE_DEFER;
|
|
}
|
|
data->larb_imu[id].dev = &plarbdev->dev;
|
|
|
|
component_match_add_release(dev, &match, release_of,
|
|
compare_of, larbnode);
|
|
}
|
|
|
|
/* Get smi-common dev from the last larb. */
|
|
smicomm_node = of_parse_phandle(larbnode, "mediatek,smi", 0);
|
|
if (!smicomm_node)
|
|
return -EINVAL;
|
|
|
|
plarbdev = of_find_device_by_node(smicomm_node);
|
|
of_node_put(smicomm_node);
|
|
data->smicomm_dev = &plarbdev->dev;
|
|
|
|
pm_runtime_enable(dev);
|
|
|
|
link = device_link_add(data->smicomm_dev, dev,
|
|
DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME);
|
|
if (!link) {
|
|
dev_err(dev, "Unable to link %s.\n", dev_name(data->smicomm_dev));
|
|
ret = -EINVAL;
|
|
goto out_runtime_disable;
|
|
}
|
|
|
|
platform_set_drvdata(pdev, data);
|
|
|
|
ret = iommu_device_sysfs_add(&data->iommu, dev, NULL,
|
|
"mtk-iommu.%pa", &ioaddr);
|
|
if (ret)
|
|
goto out_link_remove;
|
|
|
|
ret = iommu_device_register(&data->iommu, &mtk_iommu_ops, dev);
|
|
if (ret)
|
|
goto out_sysfs_remove;
|
|
|
|
spin_lock_init(&data->tlb_lock);
|
|
list_add_tail(&data->list, &m4ulist);
|
|
|
|
if (!iommu_present(&platform_bus_type)) {
|
|
ret = bus_set_iommu(&platform_bus_type, &mtk_iommu_ops);
|
|
if (ret)
|
|
goto out_list_del;
|
|
}
|
|
|
|
ret = component_master_add_with_match(dev, &mtk_iommu_com_ops, match);
|
|
if (ret)
|
|
goto out_bus_set_null;
|
|
return ret;
|
|
|
|
out_bus_set_null:
|
|
bus_set_iommu(&platform_bus_type, NULL);
|
|
out_list_del:
|
|
list_del(&data->list);
|
|
iommu_device_unregister(&data->iommu);
|
|
out_sysfs_remove:
|
|
iommu_device_sysfs_remove(&data->iommu);
|
|
out_link_remove:
|
|
device_link_remove(data->smicomm_dev, dev);
|
|
out_runtime_disable:
|
|
pm_runtime_disable(dev);
|
|
return ret;
|
|
}
|
|
|
|
static int mtk_iommu_remove(struct platform_device *pdev)
|
|
{
|
|
struct mtk_iommu_data *data = platform_get_drvdata(pdev);
|
|
|
|
iommu_device_sysfs_remove(&data->iommu);
|
|
iommu_device_unregister(&data->iommu);
|
|
|
|
if (iommu_present(&platform_bus_type))
|
|
bus_set_iommu(&platform_bus_type, NULL);
|
|
|
|
clk_disable_unprepare(data->bclk);
|
|
device_link_remove(data->smicomm_dev, &pdev->dev);
|
|
pm_runtime_disable(&pdev->dev);
|
|
devm_free_irq(&pdev->dev, data->irq, data);
|
|
component_master_del(&pdev->dev, &mtk_iommu_com_ops);
|
|
return 0;
|
|
}
|
|
|
|
static int __maybe_unused mtk_iommu_runtime_suspend(struct device *dev)
|
|
{
|
|
struct mtk_iommu_data *data = dev_get_drvdata(dev);
|
|
struct mtk_iommu_suspend_reg *reg = &data->reg;
|
|
void __iomem *base = data->base;
|
|
|
|
reg->wr_len_ctrl = readl_relaxed(base + REG_MMU_WR_LEN_CTRL);
|
|
reg->misc_ctrl = readl_relaxed(base + REG_MMU_MISC_CTRL);
|
|
reg->dcm_dis = readl_relaxed(base + REG_MMU_DCM_DIS);
|
|
reg->ctrl_reg = readl_relaxed(base + REG_MMU_CTRL_REG);
|
|
reg->int_control0 = readl_relaxed(base + REG_MMU_INT_CONTROL0);
|
|
reg->int_main_control = readl_relaxed(base + REG_MMU_INT_MAIN_CONTROL);
|
|
reg->ivrp_paddr = readl_relaxed(base + REG_MMU_IVRP_PADDR);
|
|
reg->vld_pa_rng = readl_relaxed(base + REG_MMU_VLD_PA_RNG);
|
|
clk_disable_unprepare(data->bclk);
|
|
return 0;
|
|
}
|
|
|
|
static int __maybe_unused mtk_iommu_runtime_resume(struct device *dev)
|
|
{
|
|
struct mtk_iommu_data *data = dev_get_drvdata(dev);
|
|
struct mtk_iommu_suspend_reg *reg = &data->reg;
|
|
struct mtk_iommu_domain *m4u_dom = data->m4u_dom;
|
|
void __iomem *base = data->base;
|
|
int ret;
|
|
|
|
ret = clk_prepare_enable(data->bclk);
|
|
if (ret) {
|
|
dev_err(data->dev, "Failed to enable clk(%d) in resume\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
/*
|
|
* Uppon first resume, only enable the clk and return, since the values of the
|
|
* registers are not yet set.
|
|
*/
|
|
if (!m4u_dom)
|
|
return 0;
|
|
|
|
writel_relaxed(reg->wr_len_ctrl, base + REG_MMU_WR_LEN_CTRL);
|
|
writel_relaxed(reg->misc_ctrl, base + REG_MMU_MISC_CTRL);
|
|
writel_relaxed(reg->dcm_dis, base + REG_MMU_DCM_DIS);
|
|
writel_relaxed(reg->ctrl_reg, base + REG_MMU_CTRL_REG);
|
|
writel_relaxed(reg->int_control0, base + REG_MMU_INT_CONTROL0);
|
|
writel_relaxed(reg->int_main_control, base + REG_MMU_INT_MAIN_CONTROL);
|
|
writel_relaxed(reg->ivrp_paddr, base + REG_MMU_IVRP_PADDR);
|
|
writel_relaxed(reg->vld_pa_rng, base + REG_MMU_VLD_PA_RNG);
|
|
writel(m4u_dom->cfg.arm_v7s_cfg.ttbr & MMU_PT_ADDR_MASK, base + REG_MMU_PT_BASE_ADDR);
|
|
return 0;
|
|
}
|
|
|
|
static const struct dev_pm_ops mtk_iommu_pm_ops = {
|
|
SET_RUNTIME_PM_OPS(mtk_iommu_runtime_suspend, mtk_iommu_runtime_resume, NULL)
|
|
SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
|
|
pm_runtime_force_resume)
|
|
};
|
|
|
|
static const struct mtk_iommu_plat_data mt2712_data = {
|
|
.m4u_plat = M4U_MT2712,
|
|
.flags = HAS_4GB_MODE | HAS_BCLK | HAS_VLD_PA_RNG,
|
|
.inv_sel_reg = REG_MMU_INV_SEL_GEN1,
|
|
.iova_region = single_domain,
|
|
.iova_region_nr = ARRAY_SIZE(single_domain),
|
|
.larbid_remap = {{0}, {1}, {2}, {3}, {4}, {5}, {6}, {7}},
|
|
};
|
|
|
|
static const struct mtk_iommu_plat_data mt6779_data = {
|
|
.m4u_plat = M4U_MT6779,
|
|
.flags = HAS_SUB_COMM | OUT_ORDER_WR_EN | WR_THROT_EN,
|
|
.inv_sel_reg = REG_MMU_INV_SEL_GEN2,
|
|
.iova_region = single_domain,
|
|
.iova_region_nr = ARRAY_SIZE(single_domain),
|
|
.larbid_remap = {{0}, {1}, {2}, {3}, {5}, {7, 8}, {10}, {9}},
|
|
};
|
|
|
|
static const struct mtk_iommu_plat_data mt8167_data = {
|
|
.m4u_plat = M4U_MT8167,
|
|
.flags = RESET_AXI | HAS_LEGACY_IVRP_PADDR,
|
|
.inv_sel_reg = REG_MMU_INV_SEL_GEN1,
|
|
.iova_region = single_domain,
|
|
.iova_region_nr = ARRAY_SIZE(single_domain),
|
|
.larbid_remap = {{0}, {1}, {2}}, /* Linear mapping. */
|
|
};
|
|
|
|
static const struct mtk_iommu_plat_data mt8173_data = {
|
|
.m4u_plat = M4U_MT8173,
|
|
.flags = HAS_4GB_MODE | HAS_BCLK | RESET_AXI |
|
|
HAS_LEGACY_IVRP_PADDR,
|
|
.inv_sel_reg = REG_MMU_INV_SEL_GEN1,
|
|
.iova_region = single_domain,
|
|
.iova_region_nr = ARRAY_SIZE(single_domain),
|
|
.larbid_remap = {{0}, {1}, {2}, {3}, {4}, {5}}, /* Linear mapping. */
|
|
};
|
|
|
|
static const struct mtk_iommu_plat_data mt8183_data = {
|
|
.m4u_plat = M4U_MT8183,
|
|
.flags = RESET_AXI,
|
|
.inv_sel_reg = REG_MMU_INV_SEL_GEN1,
|
|
.iova_region = single_domain,
|
|
.iova_region_nr = ARRAY_SIZE(single_domain),
|
|
.larbid_remap = {{0}, {4}, {5}, {6}, {7}, {2}, {3}, {1}},
|
|
};
|
|
|
|
static const struct mtk_iommu_plat_data mt8192_data = {
|
|
.m4u_plat = M4U_MT8192,
|
|
.flags = HAS_BCLK | HAS_SUB_COMM | OUT_ORDER_WR_EN |
|
|
WR_THROT_EN | IOVA_34_EN,
|
|
.inv_sel_reg = REG_MMU_INV_SEL_GEN2,
|
|
.iova_region = mt8192_multi_dom,
|
|
.iova_region_nr = ARRAY_SIZE(mt8192_multi_dom),
|
|
.larbid_remap = {{0}, {1}, {4, 5}, {7}, {2}, {9, 11, 19, 20},
|
|
{0, 14, 16}, {0, 13, 18, 17}},
|
|
};
|
|
|
|
static const struct of_device_id mtk_iommu_of_ids[] = {
|
|
{ .compatible = "mediatek,mt2712-m4u", .data = &mt2712_data},
|
|
{ .compatible = "mediatek,mt6779-m4u", .data = &mt6779_data},
|
|
{ .compatible = "mediatek,mt8167-m4u", .data = &mt8167_data},
|
|
{ .compatible = "mediatek,mt8173-m4u", .data = &mt8173_data},
|
|
{ .compatible = "mediatek,mt8183-m4u", .data = &mt8183_data},
|
|
{ .compatible = "mediatek,mt8192-m4u", .data = &mt8192_data},
|
|
{}
|
|
};
|
|
|
|
static struct platform_driver mtk_iommu_driver = {
|
|
.probe = mtk_iommu_probe,
|
|
.remove = mtk_iommu_remove,
|
|
.driver = {
|
|
.name = "mtk-iommu",
|
|
.of_match_table = mtk_iommu_of_ids,
|
|
.pm = &mtk_iommu_pm_ops,
|
|
}
|
|
};
|
|
module_platform_driver(mtk_iommu_driver);
|
|
|
|
MODULE_DESCRIPTION("IOMMU API for MediaTek M4U implementations");
|
|
MODULE_LICENSE("GPL v2");
|