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527d147074
We add device tree files for a couple of additional SoCs in various areas:
Allwinner R40/V40 for entertainment, Broadcom Hurricane 2 for networking,
Amlogic A113D for audio, and Renesas R-Car V3M for automotive.
As usual, lots of new boards get added based on those and other SoCs:
- Actions S500 based CubieBoard6 single-board computer
- Amlogic Meson-AXG A113D based development board
- Amlogic S912 based Khadas VIM2 single-board computer
- Amlogic S912 based Tronsmart Vega S96 set-top-box
- Allwinner H5 based NanoPi NEO Plus2 single-board computer
- Allwinner R40 based Banana Pi M2 Ultra and Berry single-board computers
- Allwinner A83T based TBS A711 Tablet
- Broadcom Hurricane 2 based Ubiquiti UniFi Switch 8
- Broadcom bcm47xx based Luxul XAP-1440/XAP-810/ABR-4500/XBR-4500
wireless access points and routers
- NXP i.MX51 based Zodiac Inflight Innovations RDU1 board
- NXP i.MX53 based GE Healthcare PPD biometric monitor
- NXP i.MX6 based Pistachio single-board computer
- NXP i.MX6 based Vining-2000 automotive diagnostic interface
- NXP i.MX6 based Ka-Ro TX6 Computer-on-Module in additional variants
- Qualcomm MSM8974 (Snapdragon 800) based Fairphone 2 phone
- Qualcomm MSM8974pro (Snapdragon 801) based Sony Xperia Z2 Tablet
- Realtek RTD1295 based set-top-boxes MeLE V9 and PROBOX2 AVA
- Renesas R-Car V3M (R8A77970) SoC and "Eagle" reference board
- Renesas H3ULCB and M3ULCB "Kingfisher" extension infotainment boards
- Renasas r8a7745 based iWave G22D-SODIMM SoM
- Rockchip rk3288 based Amarula Vyasa single-board computer
- Samsung Exynos5800 based Odroid HC1 single-board computer
For existing SoC support, there was a lot of ongoing work, as usual
most of that concentrated on the Renesas, Rockchip, OMAP, i.MX, Amlogic
and Allwinner platforms, but others were also active.
Rob Herring and many others worked on reducing the number of issues that
the latest version of 'dtc' now warns about. Unfortunately there is still
a lot left to do.
A rework of the ARM foundation model introduced several new files
for common variations of the model.
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Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM device-tree updates from Arnd Bergmann:
"We add device tree files for a couple of additional SoCs in various
areas:
Allwinner R40/V40 for entertainment, Broadcom Hurricane 2 for
networking, Amlogic A113D for audio, and Renesas R-Car V3M for
automotive.
As usual, lots of new boards get added based on those and other SoCs:
- Actions S500 based CubieBoard6 single-board computer
- Amlogic Meson-AXG A113D based development board
- Amlogic S912 based Khadas VIM2 single-board computer
- Amlogic S912 based Tronsmart Vega S96 set-top-box
- Allwinner H5 based NanoPi NEO Plus2 single-board computer
- Allwinner R40 based Banana Pi M2 Ultra and Berry single-board computers
- Allwinner A83T based TBS A711 Tablet
- Broadcom Hurricane 2 based Ubiquiti UniFi Switch 8
- Broadcom bcm47xx based Luxul XAP-1440/XAP-810/ABR-4500/XBR-4500
wireless access points and routers
- NXP i.MX51 based Zodiac Inflight Innovations RDU1 board
- NXP i.MX53 based GE Healthcare PPD biometric monitor
- NXP i.MX6 based Pistachio single-board computer
- NXP i.MX6 based Vining-2000 automotive diagnostic interface
- NXP i.MX6 based Ka-Ro TX6 Computer-on-Module in additional variants
- Qualcomm MSM8974 (Snapdragon 800) based Fairphone 2 phone
- Qualcomm MSM8974pro (Snapdragon 801) based Sony Xperia Z2 Tablet
- Realtek RTD1295 based set-top-boxes MeLE V9 and PROBOX2 AVA
- Renesas R-Car V3M (R8A77970) SoC and "Eagle" reference board
- Renesas H3ULCB and M3ULCB "Kingfisher" extension infotainment boards
- Renasas r8a7745 based iWave G22D-SODIMM SoM
- Rockchip rk3288 based Amarula Vyasa single-board computer
- Samsung Exynos5800 based Odroid HC1 single-board computer
For existing SoC support, there was a lot of ongoing work, as usual
most of that concentrated on the Renesas, Rockchip, OMAP, i.MX,
Amlogic and Allwinner platforms, but others were also active.
Rob Herring and many others worked on reducing the number of issues
that the latest version of 'dtc' now warns about. Unfortunately there
is still a lot left to do.
A rework of the ARM foundation model introduced several new files for
common variations of the model"
* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (599 commits)
arm64: dts: uniphier: route on-board device IRQ to GPIO controller for PXs3
dt-bindings: bus: Add documentation for the Technologic Systems NBUS
arm64: dts: actions: s900-bubblegum-96: Add fake uart5 clock
ARM: dts: owl-s500: Add CubieBoard6
dt-bindings: arm: actions: Add CubieBoard6
ARM: dts: owl-s500-guitar-bb-rev-b: Add fake uart3 clock
ARM: dts: owl-s500: Set power domains for CPU2 and CPU3
arm: dts: mt7623: remove unused compatible string for pio node
arm: dts: mt7623: update usb related nodes
arm: dts: mt7623: update crypto node
ARM: dts: sun8i: a711: Enable USB OTG
ARM: dts: sun8i: a711: Add regulator support
ARM: dts: sun8i: a83t: bananapi-m3: Enable AP6212 WiFi on mmc1
ARM: dts: sun8i: a83t: cubietruck-plus: Enable AP6330 WiFi on mmc1
ARM: dts: sun8i: a83t: Move mmc1 pinctrl setting to dtsi file
ARM: dts: sun8i: a83t: allwinner-h8homlet-v2: Add AXP818 regulator nodes
ARM: dts: sun8i: a83t: bananapi-m3: Add AXP813 regulator nodes
ARM: dts: sun8i: a83t: cubietruck-plus: Add AXP818 regulator nodes
ARM: dts: sunxi: Add dtsi for AXP81x PMIC
arm64: dts: allwinner: H5: Restore EMAC changes
...
792 lines
19 KiB
Plaintext
792 lines
19 KiB
Plaintext
/*
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* Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This file is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include "skeleton.dtsi"
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#include "armv7-m.dtsi"
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#include <dt-bindings/pinctrl/stm32-pinfunc.h>
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#include <dt-bindings/clock/stm32fx-clock.h>
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#include <dt-bindings/mfd/stm32f7-rcc.h>
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/ {
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clocks {
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clk_hse: clk-hse {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <0>;
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};
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clk-lse {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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};
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clk-lsi {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32000>;
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};
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clk_i2s_ckin: clk-i2s-ckin {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <48000000>;
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};
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};
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soc {
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timer2: timer@40000000 {
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compatible = "st,stm32-timer";
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reg = <0x40000000 0x400>;
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interrupts = <28>;
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clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>;
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status = "disabled";
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};
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timers2: timers@40000000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32-timers";
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reg = <0x40000000 0x400>;
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clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>;
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clock-names = "int";
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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};
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timer@1 {
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compatible = "st,stm32-timer-trigger";
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reg = <1>;
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status = "disabled";
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};
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};
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timer3: timer@40000400 {
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compatible = "st,stm32-timer";
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reg = <0x40000400 0x400>;
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interrupts = <29>;
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clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>;
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status = "disabled";
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};
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timers3: timers@40000400 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32-timers";
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reg = <0x40000400 0x400>;
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clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>;
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clock-names = "int";
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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};
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timer@2 {
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compatible = "st,stm32-timer-trigger";
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reg = <2>;
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status = "disabled";
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};
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};
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timer4: timer@40000800 {
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compatible = "st,stm32-timer";
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reg = <0x40000800 0x400>;
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interrupts = <30>;
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clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>;
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status = "disabled";
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};
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timers4: timers@40000800 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32-timers";
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reg = <0x40000800 0x400>;
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clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>;
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clock-names = "int";
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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};
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timer@3 {
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compatible = "st,stm32-timer-trigger";
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reg = <3>;
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status = "disabled";
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};
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};
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timer5: timer@40000c00 {
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compatible = "st,stm32-timer";
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reg = <0x40000c00 0x400>;
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interrupts = <50>;
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clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
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};
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timers5: timers@40000c00 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32-timers";
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reg = <0x40000C00 0x400>;
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clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
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clock-names = "int";
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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};
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timer@4 {
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compatible = "st,stm32-timer-trigger";
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reg = <4>;
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status = "disabled";
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};
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};
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timer6: timer@40001000 {
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compatible = "st,stm32-timer";
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reg = <0x40001000 0x400>;
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interrupts = <54>;
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clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>;
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status = "disabled";
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};
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timers6: timers@40001000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32-timers";
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reg = <0x40001000 0x400>;
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clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>;
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clock-names = "int";
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status = "disabled";
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timer@5 {
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compatible = "st,stm32-timer-trigger";
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reg = <5>;
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status = "disabled";
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};
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};
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timer7: timer@40001400 {
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compatible = "st,stm32-timer";
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reg = <0x40001400 0x400>;
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interrupts = <55>;
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clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>;
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status = "disabled";
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};
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timers7: timers@40001400 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32-timers";
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reg = <0x40001400 0x400>;
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clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>;
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clock-names = "int";
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status = "disabled";
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timer@6 {
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compatible = "st,stm32-timer-trigger";
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reg = <6>;
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status = "disabled";
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};
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};
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timers12: timers@40001800 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32-timers";
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reg = <0x40001800 0x400>;
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clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM12)>;
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clock-names = "int";
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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};
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timer@11 {
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compatible = "st,stm32-timer-trigger";
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reg = <11>;
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status = "disabled";
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};
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};
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timers13: timers@40001c00 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32-timers";
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reg = <0x40001C00 0x400>;
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clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM13)>;
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clock-names = "int";
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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};
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};
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timers14: timers@40002000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32-timers";
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reg = <0x40002000 0x400>;
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clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM14)>;
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clock-names = "int";
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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};
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};
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rtc: rtc@40002800 {
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compatible = "st,stm32-rtc";
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reg = <0x40002800 0x400>;
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clocks = <&rcc 1 CLK_RTC>;
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clock-names = "ck_rtc";
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assigned-clocks = <&rcc 1 CLK_RTC>;
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assigned-clock-parents = <&rcc 1 CLK_LSE>;
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interrupt-parent = <&exti>;
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interrupts = <17 1>;
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interrupt-names = "alarm";
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st,syscfg = <&pwrcfg>;
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status = "disabled";
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};
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usart2: serial@40004400 {
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compatible = "st,stm32f7-uart";
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reg = <0x40004400 0x400>;
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interrupts = <38>;
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clocks = <&rcc 1 CLK_USART2>;
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status = "disabled";
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};
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usart3: serial@40004800 {
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compatible = "st,stm32f7-uart";
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reg = <0x40004800 0x400>;
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interrupts = <39>;
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clocks = <&rcc 1 CLK_USART3>;
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status = "disabled";
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};
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usart4: serial@40004c00 {
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compatible = "st,stm32f7-uart";
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reg = <0x40004c00 0x400>;
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interrupts = <52>;
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clocks = <&rcc 1 CLK_UART4>;
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status = "disabled";
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};
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usart5: serial@40005000 {
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compatible = "st,stm32f7-uart";
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reg = <0x40005000 0x400>;
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interrupts = <53>;
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clocks = <&rcc 1 CLK_UART5>;
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status = "disabled";
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};
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i2c1: i2c@40005400 {
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compatible = "st,stm32f7-i2c";
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reg = <0x40005400 0x400>;
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interrupts = <31>,
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<32>;
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resets = <&rcc STM32F7_APB1_RESET(I2C1)>;
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clocks = <&rcc 1 CLK_I2C1>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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cec: cec@40006c00 {
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compatible = "st,stm32-cec";
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reg = <0x40006C00 0x400>;
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interrupts = <94>;
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clocks = <&rcc 0 STM32F7_APB1_CLOCK(CEC)>, <&rcc 1 CLK_HDMI_CEC>;
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clock-names = "cec", "hdmi-cec";
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status = "disabled";
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};
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usart7: serial@40007800 {
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compatible = "st,stm32f7-uart";
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reg = <0x40007800 0x400>;
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interrupts = <82>;
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clocks = <&rcc 1 CLK_UART7>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usart8: serial@40007c00 {
|
|
compatible = "st,stm32f7-uart";
|
|
reg = <0x40007c00 0x400>;
|
|
interrupts = <83>;
|
|
clocks = <&rcc 1 CLK_UART8>;
|
|
status = "disabled";
|
|
};
|
|
|
|
timers1: timers@40010000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "st,stm32-timers";
|
|
reg = <0x40010000 0x400>;
|
|
clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM1)>;
|
|
clock-names = "int";
|
|
status = "disabled";
|
|
|
|
pwm {
|
|
compatible = "st,stm32-pwm";
|
|
status = "disabled";
|
|
};
|
|
|
|
timer@0 {
|
|
compatible = "st,stm32-timer-trigger";
|
|
reg = <0>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
timers8: timers@40010400 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "st,stm32-timers";
|
|
reg = <0x40010400 0x400>;
|
|
clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM8)>;
|
|
clock-names = "int";
|
|
status = "disabled";
|
|
|
|
pwm {
|
|
compatible = "st,stm32-pwm";
|
|
status = "disabled";
|
|
};
|
|
|
|
timer@7 {
|
|
compatible = "st,stm32-timer-trigger";
|
|
reg = <7>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
usart1: serial@40011000 {
|
|
compatible = "st,stm32f7-uart";
|
|
reg = <0x40011000 0x400>;
|
|
interrupts = <37>;
|
|
clocks = <&rcc 1 CLK_USART1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usart6: serial@40011400 {
|
|
compatible = "st,stm32f7-uart";
|
|
reg = <0x40011400 0x400>;
|
|
interrupts = <71>;
|
|
clocks = <&rcc 1 CLK_USART6>;
|
|
status = "disabled";
|
|
};
|
|
|
|
syscfg: system-config@40013800 {
|
|
compatible = "syscon";
|
|
reg = <0x40013800 0x400>;
|
|
};
|
|
|
|
exti: interrupt-controller@40013c00 {
|
|
compatible = "st,stm32-exti";
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
reg = <0x40013C00 0x400>;
|
|
interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;
|
|
};
|
|
|
|
timers9: timers@40014000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "st,stm32-timers";
|
|
reg = <0x40014000 0x400>;
|
|
clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM9)>;
|
|
clock-names = "int";
|
|
status = "disabled";
|
|
|
|
pwm {
|
|
compatible = "st,stm32-pwm";
|
|
status = "disabled";
|
|
};
|
|
|
|
timer@8 {
|
|
compatible = "st,stm32-timer-trigger";
|
|
reg = <8>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
timers10: timers@40014400 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "st,stm32-timers";
|
|
reg = <0x40014400 0x400>;
|
|
clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM10)>;
|
|
clock-names = "int";
|
|
status = "disabled";
|
|
|
|
pwm {
|
|
compatible = "st,stm32-pwm";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
timers11: timers@40014800 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "st,stm32-timers";
|
|
reg = <0x40014800 0x400>;
|
|
clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM11)>;
|
|
clock-names = "int";
|
|
status = "disabled";
|
|
|
|
pwm {
|
|
compatible = "st,stm32-pwm";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
pwrcfg: power-config@40007000 {
|
|
compatible = "syscon";
|
|
reg = <0x40007000 0x400>;
|
|
};
|
|
|
|
pin-controller {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
compatible = "st,stm32f746-pinctrl";
|
|
ranges = <0 0x40020000 0x3000>;
|
|
interrupt-parent = <&exti>;
|
|
st,syscfg = <&syscfg 0x8>;
|
|
pins-are-numbered;
|
|
|
|
gpioa: gpio@40020000 {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
reg = <0x0 0x400>;
|
|
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOA)>;
|
|
st,bank-name = "GPIOA";
|
|
};
|
|
|
|
gpiob: gpio@40020400 {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
reg = <0x400 0x400>;
|
|
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOB)>;
|
|
st,bank-name = "GPIOB";
|
|
};
|
|
|
|
gpioc: gpio@40020800 {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
reg = <0x800 0x400>;
|
|
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOC)>;
|
|
st,bank-name = "GPIOC";
|
|
};
|
|
|
|
gpiod: gpio@40020c00 {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
reg = <0xc00 0x400>;
|
|
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOD)>;
|
|
st,bank-name = "GPIOD";
|
|
};
|
|
|
|
gpioe: gpio@40021000 {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
reg = <0x1000 0x400>;
|
|
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOE)>;
|
|
st,bank-name = "GPIOE";
|
|
};
|
|
|
|
gpiof: gpio@40021400 {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
reg = <0x1400 0x400>;
|
|
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOF)>;
|
|
st,bank-name = "GPIOF";
|
|
};
|
|
|
|
gpiog: gpio@40021800 {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
reg = <0x1800 0x400>;
|
|
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOG)>;
|
|
st,bank-name = "GPIOG";
|
|
};
|
|
|
|
gpioh: gpio@40021c00 {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
reg = <0x1c00 0x400>;
|
|
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOH)>;
|
|
st,bank-name = "GPIOH";
|
|
};
|
|
|
|
gpioi: gpio@40022000 {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
reg = <0x2000 0x400>;
|
|
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOI)>;
|
|
st,bank-name = "GPIOI";
|
|
};
|
|
|
|
gpioj: gpio@40022400 {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
reg = <0x2400 0x400>;
|
|
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOJ)>;
|
|
st,bank-name = "GPIOJ";
|
|
};
|
|
|
|
gpiok: gpio@40022800 {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
reg = <0x2800 0x400>;
|
|
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOK)>;
|
|
st,bank-name = "GPIOK";
|
|
};
|
|
|
|
cec_pins_a: cec@0 {
|
|
pins {
|
|
pinmux = <STM32_PINMUX('A', 15, AF4)>; /* HDMI CEC */
|
|
slew-rate = <0>;
|
|
drive-open-drain;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
usart1_pins_a: usart1@0 {
|
|
pins1 {
|
|
pinmux = <STM32_PINMUX('A', 9, AF7)>; /* USART1_TX */
|
|
bias-disable;
|
|
drive-push-pull;
|
|
slew-rate = <0>;
|
|
};
|
|
pins2 {
|
|
pinmux = <STM32_PINMUX('A', 10, AF7)>; /* USART1_RX */
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
usart1_pins_b: usart1@1 {
|
|
pins1 {
|
|
pinmux = <STM32_PINMUX('A', 9, AF7)>; /* USART1_TX */
|
|
bias-disable;
|
|
drive-push-pull;
|
|
slew-rate = <0>;
|
|
};
|
|
pins2 {
|
|
pinmux = <STM32_PINMUX('B', 7, AF7)>; /* USART1_RX */
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
i2c1_pins_b: i2c1@0 {
|
|
pins {
|
|
pinmux = <STM32_PINMUX('B', 9, AF4)>, /* I2C1 SDA */
|
|
<STM32_PINMUX('B', 8, AF4)>; /* I2C1 SCL */
|
|
bias-disable;
|
|
drive-open-drain;
|
|
slew-rate = <0>;
|
|
};
|
|
};
|
|
|
|
usbotg_hs_pins_a: usbotg-hs@0 {
|
|
pins {
|
|
pinmux = <STM32_PINMUX('H', 4, AF10)>, /* OTG_HS_ULPI_NXT */
|
|
<STM32_PINMUX('I', 11, AF10)>, /* OTG_HS_ULPI_DIR */
|
|
<STM32_PINMUX('C', 0, AF10)>, /* OTG_HS_ULPI_STP */
|
|
<STM32_PINMUX('A', 5, AF10)>, /* OTG_HS_ULPI_CK */
|
|
<STM32_PINMUX('A', 3, AF10)>, /* OTG_HS_ULPI_D0 */
|
|
<STM32_PINMUX('B', 0, AF10)>, /* OTG_HS_ULPI_D1 */
|
|
<STM32_PINMUX('B', 1, AF10)>, /* OTG_HS_ULPI_D2 */
|
|
<STM32_PINMUX('B', 10, AF10)>, /* OTG_HS_ULPI_D3 */
|
|
<STM32_PINMUX('B', 11, AF10)>, /* OTG_HS_ULPI_D4 */
|
|
<STM32_PINMUX('B', 12, AF10)>, /* OTG_HS_ULPI_D5 */
|
|
<STM32_PINMUX('B', 13, AF10)>, /* OTG_HS_ULPI_D6 */
|
|
<STM32_PINMUX('B', 5, AF10)>; /* OTG_HS_ULPI_D7 */
|
|
bias-disable;
|
|
drive-push-pull;
|
|
slew-rate = <2>;
|
|
};
|
|
};
|
|
|
|
usbotg_hs_pins_b: usbotg-hs@1 {
|
|
pins {
|
|
pinmux = <STM32_PINMUX('H', 4, AF10)>, /* OTG_HS_ULPI_NXT */
|
|
<STM32_PINMUX('C', 2, AF10)>, /* OTG_HS_ULPI_DIR */
|
|
<STM32_PINMUX('C', 0, AF10)>, /* OTG_HS_ULPI_STP */
|
|
<STM32_PINMUX('A', 5, AF10)>, /* OTG_HS_ULPI_CK */
|
|
<STM32_PINMUX('A', 3, AF10)>, /* OTG_HS_ULPI_D0 */
|
|
<STM32_PINMUX('B', 0, AF10)>, /* OTG_HS_ULPI_D1 */
|
|
<STM32_PINMUX('B', 1, AF10)>, /* OTG_HS_ULPI_D2 */
|
|
<STM32_PINMUX('B', 10, AF10)>, /* OTG_HS_ULPI_D3 */
|
|
<STM32_PINMUX('B', 11, AF10)>, /* OTG_HS_ULPI_D4 */
|
|
<STM32_PINMUX('B', 12, AF10)>, /* OTG_HS_ULPI_D5 */
|
|
<STM32_PINMUX('B', 13, AF10)>, /* OTG_HS_ULPI_D6 */
|
|
<STM32_PINMUX('B', 5, AF10)>; /* OTG_HS_ULPI_D7 */
|
|
bias-disable;
|
|
drive-push-pull;
|
|
slew-rate = <2>;
|
|
};
|
|
};
|
|
|
|
usbotg_fs_pins_a: usbotg-fs@0 {
|
|
pins {
|
|
pinmux = <STM32_PINMUX('A', 10, AF10)>, /* OTG_FS_ID */
|
|
<STM32_PINMUX('A', 11, AF10)>, /* OTG_FS_DM */
|
|
<STM32_PINMUX('A', 12, AF10)>; /* OTG_FS_DP */
|
|
bias-disable;
|
|
drive-push-pull;
|
|
slew-rate = <2>;
|
|
};
|
|
};
|
|
};
|
|
|
|
crc: crc@40023000 {
|
|
compatible = "st,stm32f7-crc";
|
|
reg = <0x40023000 0x400>;
|
|
clocks = <&rcc 0 12>;
|
|
status = "disabled";
|
|
};
|
|
|
|
rcc: rcc@40023800 {
|
|
#reset-cells = <1>;
|
|
#clock-cells = <2>;
|
|
compatible = "st,stm32f746-rcc", "st,stm32-rcc";
|
|
reg = <0x40023800 0x400>;
|
|
clocks = <&clk_hse>, <&clk_i2s_ckin>;
|
|
st,syscfg = <&pwrcfg>;
|
|
assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
|
|
assigned-clock-rates = <1000000>;
|
|
};
|
|
|
|
dma1: dma@40026000 {
|
|
compatible = "st,stm32-dma";
|
|
reg = <0x40026000 0x400>;
|
|
interrupts = <11>,
|
|
<12>,
|
|
<13>,
|
|
<14>,
|
|
<15>,
|
|
<16>,
|
|
<17>,
|
|
<47>;
|
|
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA1)>;
|
|
#dma-cells = <4>;
|
|
status = "disabled";
|
|
};
|
|
|
|
dma2: dma@40026400 {
|
|
compatible = "st,stm32-dma";
|
|
reg = <0x40026400 0x400>;
|
|
interrupts = <56>,
|
|
<57>,
|
|
<58>,
|
|
<59>,
|
|
<60>,
|
|
<68>,
|
|
<69>,
|
|
<70>;
|
|
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA2)>;
|
|
#dma-cells = <4>;
|
|
st,mem2mem;
|
|
status = "disabled";
|
|
};
|
|
|
|
usbotg_hs: usb@40040000 {
|
|
compatible = "st,stm32f7-hsotg";
|
|
reg = <0x40040000 0x40000>;
|
|
interrupts = <77>;
|
|
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHS)>;
|
|
clock-names = "otg";
|
|
status = "disabled";
|
|
};
|
|
|
|
usbotg_fs: usb@50000000 {
|
|
compatible = "st,stm32f4x9-fsotg";
|
|
reg = <0x50000000 0x40000>;
|
|
interrupts = <67>;
|
|
clocks = <&rcc 0 STM32F7_AHB2_CLOCK(OTGFS)>;
|
|
clock-names = "otg";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
};
|
|
|
|
&systick {
|
|
clocks = <&rcc 1 0>;
|
|
status = "okay";
|
|
};
|