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13dccb9e65
This merges the 32-bit and 64-bit implementations of pci_process_bridge_OF_ranges(). The new function is cleaner than both the old ones, and supports 64 bits ranges on ppc32 which is necessary for the 4xx port. It also adds some better (hopefully) output to the kernel log which should help diagnose problems and makes better use of existing OF parsing helpers (avoiding a few bugs of both implementations along the way). There are still a few unfortunate ifdef's but there is no way around these for now at least not until some other bits of the PCI code are made common. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
642 lines
18 KiB
C
642 lines
18 KiB
C
/*
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* Contains common pci routines for ALL ppc platform
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* (based on pci_32.c and pci_64.c)
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*
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* Port for PPC64 David Engebretsen, IBM Corp.
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* Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
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*
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* Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
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* Rework, based on alpha PCI code.
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*
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* Common pmac/prep/chrp pci routines. -- Cort
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#undef DEBUG
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/string.h>
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#include <linux/init.h>
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#include <linux/bootmem.h>
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#include <linux/mm.h>
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#include <linux/list.h>
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#include <linux/syscalls.h>
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#include <linux/irq.h>
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#include <linux/vmalloc.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include <asm/prom.h>
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#include <asm/pci-bridge.h>
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#include <asm/byteorder.h>
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#include <asm/machdep.h>
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#include <asm/ppc-pci.h>
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#include <asm/firmware.h>
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#ifdef DEBUG
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#include <asm/udbg.h>
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#define DBG(fmt...) printk(fmt)
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#else
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#define DBG(fmt...)
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#endif
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static DEFINE_SPINLOCK(hose_spinlock);
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/* XXX kill that some day ... */
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static int global_phb_number; /* Global phb counter */
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/* ISA Memory physical address */
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resource_size_t isa_mem_base;
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struct pci_controller *pcibios_alloc_controller(struct device_node *dev)
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{
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struct pci_controller *phb;
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phb = zalloc_maybe_bootmem(sizeof(struct pci_controller), GFP_KERNEL);
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if (phb == NULL)
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return NULL;
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spin_lock(&hose_spinlock);
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phb->global_number = global_phb_number++;
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list_add_tail(&phb->list_node, &hose_list);
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spin_unlock(&hose_spinlock);
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phb->dn = dev;
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phb->is_dynamic = mem_init_done;
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#ifdef CONFIG_PPC64
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if (dev) {
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int nid = of_node_to_nid(dev);
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if (nid < 0 || !node_online(nid))
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nid = -1;
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PHB_SET_NODE(phb, nid);
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}
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#endif
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return phb;
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}
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void pcibios_free_controller(struct pci_controller *phb)
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{
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spin_lock(&hose_spinlock);
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list_del(&phb->list_node);
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spin_unlock(&hose_spinlock);
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if (phb->is_dynamic)
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kfree(phb);
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}
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int pcibios_vaddr_is_ioport(void __iomem *address)
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{
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int ret = 0;
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struct pci_controller *hose;
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unsigned long size;
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spin_lock(&hose_spinlock);
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list_for_each_entry(hose, &hose_list, list_node) {
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#ifdef CONFIG_PPC64
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size = hose->pci_io_size;
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#else
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size = hose->io_resource.end - hose->io_resource.start + 1;
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#endif
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if (address >= hose->io_base_virt &&
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address < (hose->io_base_virt + size)) {
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ret = 1;
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break;
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}
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}
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spin_unlock(&hose_spinlock);
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return ret;
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}
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/*
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* Return the domain number for this bus.
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*/
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int pci_domain_nr(struct pci_bus *bus)
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{
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struct pci_controller *hose = pci_bus_to_host(bus);
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return hose->global_number;
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}
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EXPORT_SYMBOL(pci_domain_nr);
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#ifdef CONFIG_PPC_OF
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/* This routine is meant to be used early during boot, when the
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* PCI bus numbers have not yet been assigned, and you need to
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* issue PCI config cycles to an OF device.
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* It could also be used to "fix" RTAS config cycles if you want
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* to set pci_assign_all_buses to 1 and still use RTAS for PCI
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* config cycles.
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*/
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struct pci_controller* pci_find_hose_for_OF_device(struct device_node* node)
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{
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if (!have_of)
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return NULL;
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while(node) {
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struct pci_controller *hose, *tmp;
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list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
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if (hose->dn == node)
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return hose;
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node = node->parent;
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}
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return NULL;
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}
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static ssize_t pci_show_devspec(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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struct pci_dev *pdev;
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struct device_node *np;
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pdev = to_pci_dev (dev);
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np = pci_device_to_OF_node(pdev);
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if (np == NULL || np->full_name == NULL)
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return 0;
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return sprintf(buf, "%s", np->full_name);
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}
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static DEVICE_ATTR(devspec, S_IRUGO, pci_show_devspec, NULL);
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#endif /* CONFIG_PPC_OF */
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/* Add sysfs properties */
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int pcibios_add_platform_entries(struct pci_dev *pdev)
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{
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#ifdef CONFIG_PPC_OF
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return device_create_file(&pdev->dev, &dev_attr_devspec);
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#else
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return 0;
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#endif /* CONFIG_PPC_OF */
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}
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char __devinit *pcibios_setup(char *str)
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{
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return str;
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}
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/*
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* Reads the interrupt pin to determine if interrupt is use by card.
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* If the interrupt is used, then gets the interrupt line from the
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* openfirmware and sets it in the pci_dev and pci_config line.
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*/
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int pci_read_irq_line(struct pci_dev *pci_dev)
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{
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struct of_irq oirq;
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unsigned int virq;
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DBG("Try to map irq for %s...\n", pci_name(pci_dev));
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#ifdef DEBUG
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memset(&oirq, 0xff, sizeof(oirq));
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#endif
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/* Try to get a mapping from the device-tree */
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if (of_irq_map_pci(pci_dev, &oirq)) {
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u8 line, pin;
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/* If that fails, lets fallback to what is in the config
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* space and map that through the default controller. We
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* also set the type to level low since that's what PCI
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* interrupts are. If your platform does differently, then
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* either provide a proper interrupt tree or don't use this
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* function.
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*/
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if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &pin))
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return -1;
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if (pin == 0)
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return -1;
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if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_LINE, &line) ||
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line == 0xff) {
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return -1;
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}
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DBG(" -> no map ! Using irq line %d from PCI config\n", line);
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virq = irq_create_mapping(NULL, line);
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if (virq != NO_IRQ)
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set_irq_type(virq, IRQ_TYPE_LEVEL_LOW);
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} else {
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DBG(" -> got one, spec %d cells (0x%08x 0x%08x...) on %s\n",
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oirq.size, oirq.specifier[0], oirq.specifier[1],
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oirq.controller->full_name);
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virq = irq_create_of_mapping(oirq.controller, oirq.specifier,
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oirq.size);
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}
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if(virq == NO_IRQ) {
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DBG(" -> failed to map !\n");
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return -1;
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}
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DBG(" -> mapped to linux irq %d\n", virq);
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pci_dev->irq = virq;
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return 0;
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}
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EXPORT_SYMBOL(pci_read_irq_line);
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/*
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* Platform support for /proc/bus/pci/X/Y mmap()s,
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* modelled on the sparc64 implementation by Dave Miller.
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* -- paulus.
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*/
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/*
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* Adjust vm_pgoff of VMA such that it is the physical page offset
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* corresponding to the 32-bit pci bus offset for DEV requested by the user.
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*
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* Basically, the user finds the base address for his device which he wishes
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* to mmap. They read the 32-bit value from the config space base register,
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* add whatever PAGE_SIZE multiple offset they wish, and feed this into the
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* offset parameter of mmap on /proc/bus/pci/XXX for that device.
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*
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* Returns negative error code on failure, zero on success.
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*/
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static struct resource *__pci_mmap_make_offset(struct pci_dev *dev,
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resource_size_t *offset,
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enum pci_mmap_state mmap_state)
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{
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struct pci_controller *hose = pci_bus_to_host(dev->bus);
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unsigned long io_offset = 0;
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int i, res_bit;
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if (hose == 0)
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return NULL; /* should never happen */
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/* If memory, add on the PCI bridge address offset */
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if (mmap_state == pci_mmap_mem) {
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#if 0 /* See comment in pci_resource_to_user() for why this is disabled */
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*offset += hose->pci_mem_offset;
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#endif
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res_bit = IORESOURCE_MEM;
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} else {
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io_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
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*offset += io_offset;
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res_bit = IORESOURCE_IO;
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}
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/*
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* Check that the offset requested corresponds to one of the
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* resources of the device.
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*/
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for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
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struct resource *rp = &dev->resource[i];
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int flags = rp->flags;
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/* treat ROM as memory (should be already) */
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if (i == PCI_ROM_RESOURCE)
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flags |= IORESOURCE_MEM;
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/* Active and same type? */
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if ((flags & res_bit) == 0)
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continue;
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/* In the range of this resource? */
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if (*offset < (rp->start & PAGE_MASK) || *offset > rp->end)
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continue;
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/* found it! construct the final physical address */
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if (mmap_state == pci_mmap_io)
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*offset += hose->io_base_phys - io_offset;
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return rp;
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}
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return NULL;
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}
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/*
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* Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
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* device mapping.
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*/
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static pgprot_t __pci_mmap_set_pgprot(struct pci_dev *dev, struct resource *rp,
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pgprot_t protection,
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enum pci_mmap_state mmap_state,
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int write_combine)
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{
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unsigned long prot = pgprot_val(protection);
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/* Write combine is always 0 on non-memory space mappings. On
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* memory space, if the user didn't pass 1, we check for a
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* "prefetchable" resource. This is a bit hackish, but we use
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* this to workaround the inability of /sysfs to provide a write
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* combine bit
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*/
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if (mmap_state != pci_mmap_mem)
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write_combine = 0;
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else if (write_combine == 0) {
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if (rp->flags & IORESOURCE_PREFETCH)
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write_combine = 1;
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}
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/* XXX would be nice to have a way to ask for write-through */
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prot |= _PAGE_NO_CACHE;
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if (write_combine)
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prot &= ~_PAGE_GUARDED;
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else
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prot |= _PAGE_GUARDED;
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return __pgprot(prot);
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}
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/*
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* This one is used by /dev/mem and fbdev who have no clue about the
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* PCI device, it tries to find the PCI device first and calls the
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* above routine
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*/
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pgprot_t pci_phys_mem_access_prot(struct file *file,
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unsigned long pfn,
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unsigned long size,
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pgprot_t protection)
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{
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struct pci_dev *pdev = NULL;
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struct resource *found = NULL;
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unsigned long prot = pgprot_val(protection);
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unsigned long offset = pfn << PAGE_SHIFT;
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int i;
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if (page_is_ram(pfn))
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return __pgprot(prot);
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prot |= _PAGE_NO_CACHE | _PAGE_GUARDED;
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for_each_pci_dev(pdev) {
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for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
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struct resource *rp = &pdev->resource[i];
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int flags = rp->flags;
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/* Active and same type? */
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if ((flags & IORESOURCE_MEM) == 0)
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continue;
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/* In the range of this resource? */
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if (offset < (rp->start & PAGE_MASK) ||
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offset > rp->end)
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continue;
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found = rp;
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break;
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}
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if (found)
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break;
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}
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if (found) {
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if (found->flags & IORESOURCE_PREFETCH)
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prot &= ~_PAGE_GUARDED;
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pci_dev_put(pdev);
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}
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DBG("non-PCI map for %lx, prot: %lx\n", offset, prot);
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return __pgprot(prot);
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}
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/*
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* Perform the actual remap of the pages for a PCI device mapping, as
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* appropriate for this architecture. The region in the process to map
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* is described by vm_start and vm_end members of VMA, the base physical
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* address is found in vm_pgoff.
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* The pci device structure is provided so that architectures may make mapping
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* decisions on a per-device or per-bus basis.
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*
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* Returns a negative error code on failure, zero on success.
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*/
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int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
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enum pci_mmap_state mmap_state, int write_combine)
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{
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resource_size_t offset = vma->vm_pgoff << PAGE_SHIFT;
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struct resource *rp;
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int ret;
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rp = __pci_mmap_make_offset(dev, &offset, mmap_state);
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if (rp == NULL)
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return -EINVAL;
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vma->vm_pgoff = offset >> PAGE_SHIFT;
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vma->vm_page_prot = __pci_mmap_set_pgprot(dev, rp,
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vma->vm_page_prot,
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mmap_state, write_combine);
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ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
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vma->vm_end - vma->vm_start, vma->vm_page_prot);
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return ret;
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}
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void pci_resource_to_user(const struct pci_dev *dev, int bar,
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const struct resource *rsrc,
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resource_size_t *start, resource_size_t *end)
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{
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struct pci_controller *hose = pci_bus_to_host(dev->bus);
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resource_size_t offset = 0;
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if (hose == NULL)
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return;
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if (rsrc->flags & IORESOURCE_IO)
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offset = (unsigned long)hose->io_base_virt - _IO_BASE;
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/* We pass a fully fixed up address to userland for MMIO instead of
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* a BAR value because X is lame and expects to be able to use that
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* to pass to /dev/mem !
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*
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* That means that we'll have potentially 64 bits values where some
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* userland apps only expect 32 (like X itself since it thinks only
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* Sparc has 64 bits MMIO) but if we don't do that, we break it on
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* 32 bits CHRPs :-(
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*
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* Hopefully, the sysfs insterface is immune to that gunk. Once X
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* has been fixed (and the fix spread enough), we can re-enable the
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* 2 lines below and pass down a BAR value to userland. In that case
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* we'll also have to re-enable the matching code in
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* __pci_mmap_make_offset().
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*
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* BenH.
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*/
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#if 0
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else if (rsrc->flags & IORESOURCE_MEM)
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offset = hose->pci_mem_offset;
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#endif
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*start = rsrc->start - offset;
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*end = rsrc->end - offset;
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}
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/**
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* pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree
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* @hose: newly allocated pci_controller to be setup
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* @dev: device node of the host bridge
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* @primary: set if primary bus (32 bits only, soon to be deprecated)
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*
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* This function will parse the "ranges" property of a PCI host bridge device
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* node and setup the resource mapping of a pci controller based on its
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* content.
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*
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* Life would be boring if it wasn't for a few issues that we have to deal
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* with here:
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*
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* - We can only cope with one IO space range and up to 3 Memory space
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* ranges. However, some machines (thanks Apple !) tend to split their
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* space into lots of small contiguous ranges. So we have to coalesce.
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*
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* - We can only cope with all memory ranges having the same offset
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* between CPU addresses and PCI addresses. Unfortunately, some bridges
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* are setup for a large 1:1 mapping along with a small "window" which
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* maps PCI address 0 to some arbitrary high address of the CPU space in
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* order to give access to the ISA memory hole.
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* The way out of here that I've chosen for now is to always set the
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* offset based on the first resource found, then override it if we
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* have a different offset and the previous was set by an ISA hole.
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*
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* - Some busses have IO space not starting at 0, which causes trouble with
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* the way we do our IO resource renumbering. The code somewhat deals with
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* it for 64 bits but I would expect problems on 32 bits.
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*
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* - Some 32 bits platforms such as 4xx can have physical space larger than
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* 32 bits so we need to use 64 bits values for the parsing
|
|
*/
|
|
void __devinit pci_process_bridge_OF_ranges(struct pci_controller *hose,
|
|
struct device_node *dev,
|
|
int primary)
|
|
{
|
|
const u32 *ranges;
|
|
int rlen;
|
|
int pna = of_n_addr_cells(dev);
|
|
int np = pna + 5;
|
|
int memno = 0, isa_hole = -1;
|
|
u32 pci_space;
|
|
unsigned long long pci_addr, cpu_addr, pci_next, cpu_next, size;
|
|
unsigned long long isa_mb = 0;
|
|
struct resource *res;
|
|
|
|
printk(KERN_INFO "PCI host bridge %s %s ranges:\n",
|
|
dev->full_name, primary ? "(primary)" : "");
|
|
|
|
/* Get ranges property */
|
|
ranges = of_get_property(dev, "ranges", &rlen);
|
|
if (ranges == NULL)
|
|
return;
|
|
|
|
/* Parse it */
|
|
while ((rlen -= np * 4) >= 0) {
|
|
/* Read next ranges element */
|
|
pci_space = ranges[0];
|
|
pci_addr = of_read_number(ranges + 1, 2);
|
|
cpu_addr = of_translate_address(dev, ranges + 3);
|
|
size = of_read_number(ranges + pna + 3, 2);
|
|
ranges += np;
|
|
if (cpu_addr == OF_BAD_ADDR || size == 0)
|
|
continue;
|
|
|
|
/* Now consume following elements while they are contiguous */
|
|
for (; rlen >= np * sizeof(u32);
|
|
ranges += np, rlen -= np * 4) {
|
|
if (ranges[0] != pci_space)
|
|
break;
|
|
pci_next = of_read_number(ranges + 1, 2);
|
|
cpu_next = of_translate_address(dev, ranges + 3);
|
|
if (pci_next != pci_addr + size ||
|
|
cpu_next != cpu_addr + size)
|
|
break;
|
|
size += of_read_number(ranges + pna + 3, 2);
|
|
}
|
|
|
|
/* Act based on address space type */
|
|
res = NULL;
|
|
switch ((pci_space >> 24) & 0x3) {
|
|
case 1: /* PCI IO space */
|
|
printk(KERN_INFO
|
|
" IO 0x%016llx..0x%016llx -> 0x%016llx\n",
|
|
cpu_addr, cpu_addr + size - 1, pci_addr);
|
|
|
|
/* We support only one IO range */
|
|
if (hose->pci_io_size) {
|
|
printk(KERN_INFO
|
|
" \\--> Skipped (too many) !\n");
|
|
continue;
|
|
}
|
|
#ifdef CONFIG_PPC32
|
|
/* On 32 bits, limit I/O space to 16MB */
|
|
if (size > 0x01000000)
|
|
size = 0x01000000;
|
|
|
|
/* 32 bits needs to map IOs here */
|
|
hose->io_base_virt = ioremap(cpu_addr, size);
|
|
|
|
/* Expect trouble if pci_addr is not 0 */
|
|
if (primary)
|
|
isa_io_base =
|
|
(unsigned long)hose->io_base_virt;
|
|
#endif /* CONFIG_PPC32 */
|
|
/* pci_io_size and io_base_phys always represent IO
|
|
* space starting at 0 so we factor in pci_addr
|
|
*/
|
|
hose->pci_io_size = pci_addr + size;
|
|
hose->io_base_phys = cpu_addr - pci_addr;
|
|
|
|
/* Build resource */
|
|
res = &hose->io_resource;
|
|
res->flags = IORESOURCE_IO;
|
|
res->start = pci_addr;
|
|
break;
|
|
case 2: /* PCI Memory space */
|
|
printk(KERN_INFO
|
|
" MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n",
|
|
cpu_addr, cpu_addr + size - 1, pci_addr,
|
|
(pci_space & 0x40000000) ? "Prefetch" : "");
|
|
|
|
/* We support only 3 memory ranges */
|
|
if (memno >= 3) {
|
|
printk(KERN_INFO
|
|
" \\--> Skipped (too many) !\n");
|
|
continue;
|
|
}
|
|
/* Handles ISA memory hole space here */
|
|
if (pci_addr == 0) {
|
|
isa_mb = cpu_addr;
|
|
isa_hole = memno;
|
|
if (primary || isa_mem_base == 0)
|
|
isa_mem_base = cpu_addr;
|
|
}
|
|
|
|
/* We get the PCI/Mem offset from the first range or
|
|
* the, current one if the offset came from an ISA
|
|
* hole. If they don't match, bugger.
|
|
*/
|
|
if (memno == 0 ||
|
|
(isa_hole >= 0 && pci_addr != 0 &&
|
|
hose->pci_mem_offset == isa_mb))
|
|
hose->pci_mem_offset = cpu_addr - pci_addr;
|
|
else if (pci_addr != 0 &&
|
|
hose->pci_mem_offset != cpu_addr - pci_addr) {
|
|
printk(KERN_INFO
|
|
" \\--> Skipped (offset mismatch) !\n");
|
|
continue;
|
|
}
|
|
|
|
/* Build resource */
|
|
res = &hose->mem_resources[memno++];
|
|
res->flags = IORESOURCE_MEM;
|
|
if (pci_space & 0x40000000)
|
|
res->flags |= IORESOURCE_PREFETCH;
|
|
res->start = cpu_addr;
|
|
break;
|
|
}
|
|
if (res != NULL) {
|
|
res->name = dev->full_name;
|
|
res->end = res->start + size - 1;
|
|
res->parent = NULL;
|
|
res->sibling = NULL;
|
|
res->child = NULL;
|
|
}
|
|
}
|
|
|
|
/* Out of paranoia, let's put the ISA hole last if any */
|
|
if (isa_hole >= 0 && memno > 0 && isa_hole != (memno-1)) {
|
|
struct resource tmp = hose->mem_resources[isa_hole];
|
|
hose->mem_resources[isa_hole] = hose->mem_resources[memno-1];
|
|
hose->mem_resources[memno-1] = tmp;
|
|
}
|
|
}
|