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aabdfd6adb
Cc: uclinux-dist-devel@blackfin.uclinux.org Cc: Anant Gole <anantgole@ti.com> Cc: Chris Elston <celston@katalix.com> Cc: Sebastian Haas <haas@ems-wuensche.com> Cc: Matthias Fuchs <matthias.fuchs@esd.eu> Signed-off-by: Wolfgang Grandegger <wg@grandegger.com> Acked-by: Sebastian Haas <dev@sebastianhaas.info> Acked-by: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
723 lines
18 KiB
C
723 lines
18 KiB
C
/*
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* CAN bus driver for the alone generic (as possible as) MSCAN controller.
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*
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* Copyright (C) 2005-2006 Andrey Volkov <avolkov@varma-el.com>,
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* Varma Electronics Oy
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* Copyright (C) 2008-2009 Wolfgang Grandegger <wg@grandegger.com>
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* Copyright (C) 2008-2009 Pengutronix <kernel@pengutronix.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the version 2 of the GNU General Public License
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* as published by the Free Software Foundation
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/interrupt.h>
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#include <linux/delay.h>
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#include <linux/netdevice.h>
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#include <linux/if_arp.h>
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#include <linux/if_ether.h>
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#include <linux/list.h>
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#include <linux/can/dev.h>
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#include <linux/can/error.h>
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#include <linux/io.h>
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#include "mscan.h"
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static struct can_bittiming_const mscan_bittiming_const = {
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.name = "mscan",
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.tseg1_min = 4,
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.tseg1_max = 16,
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.tseg2_min = 2,
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.tseg2_max = 8,
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.sjw_max = 4,
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.brp_min = 1,
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.brp_max = 64,
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.brp_inc = 1,
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};
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struct mscan_state {
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u8 mode;
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u8 canrier;
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u8 cantier;
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};
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static enum can_state state_map[] = {
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CAN_STATE_ERROR_ACTIVE,
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CAN_STATE_ERROR_WARNING,
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CAN_STATE_ERROR_PASSIVE,
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CAN_STATE_BUS_OFF
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};
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static int mscan_set_mode(struct net_device *dev, u8 mode)
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{
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struct mscan_priv *priv = netdev_priv(dev);
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struct mscan_regs __iomem *regs = priv->reg_base;
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int ret = 0;
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int i;
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u8 canctl1;
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if (mode != MSCAN_NORMAL_MODE) {
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if (priv->tx_active) {
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/* Abort transfers before going to sleep */#
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out_8(®s->cantarq, priv->tx_active);
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/* Suppress TX done interrupts */
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out_8(®s->cantier, 0);
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}
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canctl1 = in_8(®s->canctl1);
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if ((mode & MSCAN_SLPRQ) && !(canctl1 & MSCAN_SLPAK)) {
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setbits8(®s->canctl0, MSCAN_SLPRQ);
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for (i = 0; i < MSCAN_SET_MODE_RETRIES; i++) {
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if (in_8(®s->canctl1) & MSCAN_SLPAK)
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break;
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udelay(100);
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}
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/*
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* The mscan controller will fail to enter sleep mode,
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* while there are irregular activities on bus, like
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* somebody keeps retransmitting. This behavior is
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* undocumented and seems to differ between mscan built
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* in mpc5200b and mpc5200. We proceed in that case,
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* since otherwise the slprq will be kept set and the
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* controller will get stuck. NOTE: INITRQ or CSWAI
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* will abort all active transmit actions, if still
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* any, at once.
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*/
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if (i >= MSCAN_SET_MODE_RETRIES)
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netdev_dbg(dev,
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"device failed to enter sleep mode. "
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"We proceed anyhow.\n");
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else
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priv->can.state = CAN_STATE_SLEEPING;
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}
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if ((mode & MSCAN_INITRQ) && !(canctl1 & MSCAN_INITAK)) {
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setbits8(®s->canctl0, MSCAN_INITRQ);
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for (i = 0; i < MSCAN_SET_MODE_RETRIES; i++) {
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if (in_8(®s->canctl1) & MSCAN_INITAK)
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break;
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}
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if (i >= MSCAN_SET_MODE_RETRIES)
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ret = -ENODEV;
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}
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if (!ret)
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priv->can.state = CAN_STATE_STOPPED;
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if (mode & MSCAN_CSWAI)
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setbits8(®s->canctl0, MSCAN_CSWAI);
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} else {
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canctl1 = in_8(®s->canctl1);
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if (canctl1 & (MSCAN_SLPAK | MSCAN_INITAK)) {
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clrbits8(®s->canctl0, MSCAN_SLPRQ | MSCAN_INITRQ);
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for (i = 0; i < MSCAN_SET_MODE_RETRIES; i++) {
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canctl1 = in_8(®s->canctl1);
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if (!(canctl1 & (MSCAN_INITAK | MSCAN_SLPAK)))
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break;
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}
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if (i >= MSCAN_SET_MODE_RETRIES)
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ret = -ENODEV;
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else
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priv->can.state = CAN_STATE_ERROR_ACTIVE;
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}
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}
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return ret;
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}
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static int mscan_start(struct net_device *dev)
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{
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struct mscan_priv *priv = netdev_priv(dev);
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struct mscan_regs __iomem *regs = priv->reg_base;
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u8 canrflg;
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int err;
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out_8(®s->canrier, 0);
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INIT_LIST_HEAD(&priv->tx_head);
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priv->prev_buf_id = 0;
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priv->cur_pri = 0;
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priv->tx_active = 0;
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priv->shadow_canrier = 0;
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priv->flags = 0;
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if (priv->type == MSCAN_TYPE_MPC5121) {
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/* Clear pending bus-off condition */
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if (in_8(®s->canmisc) & MSCAN_BOHOLD)
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out_8(®s->canmisc, MSCAN_BOHOLD);
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}
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err = mscan_set_mode(dev, MSCAN_NORMAL_MODE);
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if (err)
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return err;
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canrflg = in_8(®s->canrflg);
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priv->shadow_statflg = canrflg & MSCAN_STAT_MSK;
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priv->can.state = state_map[max(MSCAN_STATE_RX(canrflg),
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MSCAN_STATE_TX(canrflg))];
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out_8(®s->cantier, 0);
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/* Enable receive interrupts. */
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out_8(®s->canrier, MSCAN_RX_INTS_ENABLE);
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return 0;
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}
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static int mscan_restart(struct net_device *dev)
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{
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struct mscan_priv *priv = netdev_priv(dev);
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if (priv->type == MSCAN_TYPE_MPC5121) {
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struct mscan_regs __iomem *regs = priv->reg_base;
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priv->can.state = CAN_STATE_ERROR_ACTIVE;
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WARN(!(in_8(®s->canmisc) & MSCAN_BOHOLD),
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"bus-off state expected\n");
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out_8(®s->canmisc, MSCAN_BOHOLD);
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/* Re-enable receive interrupts. */
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out_8(®s->canrier, MSCAN_RX_INTS_ENABLE);
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} else {
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if (priv->can.state <= CAN_STATE_BUS_OFF)
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mscan_set_mode(dev, MSCAN_INIT_MODE);
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return mscan_start(dev);
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}
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return 0;
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}
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static netdev_tx_t mscan_start_xmit(struct sk_buff *skb, struct net_device *dev)
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{
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struct can_frame *frame = (struct can_frame *)skb->data;
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struct mscan_priv *priv = netdev_priv(dev);
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struct mscan_regs __iomem *regs = priv->reg_base;
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int i, rtr, buf_id;
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u32 can_id;
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if (can_dropped_invalid_skb(dev, skb))
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return NETDEV_TX_OK;
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out_8(®s->cantier, 0);
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i = ~priv->tx_active & MSCAN_TXE;
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buf_id = ffs(i) - 1;
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switch (hweight8(i)) {
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case 0:
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netif_stop_queue(dev);
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netdev_err(dev, "Tx Ring full when queue awake!\n");
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return NETDEV_TX_BUSY;
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case 1:
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/*
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* if buf_id < 3, then current frame will be send out of order,
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* since buffer with lower id have higher priority (hell..)
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*/
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netif_stop_queue(dev);
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case 2:
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if (buf_id < priv->prev_buf_id) {
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priv->cur_pri++;
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if (priv->cur_pri == 0xff) {
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set_bit(F_TX_WAIT_ALL, &priv->flags);
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netif_stop_queue(dev);
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}
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}
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set_bit(F_TX_PROGRESS, &priv->flags);
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break;
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}
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priv->prev_buf_id = buf_id;
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out_8(®s->cantbsel, i);
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rtr = frame->can_id & CAN_RTR_FLAG;
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/* RTR is always the lowest bit of interest, then IDs follow */
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if (frame->can_id & CAN_EFF_FLAG) {
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can_id = (frame->can_id & CAN_EFF_MASK)
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<< (MSCAN_EFF_RTR_SHIFT + 1);
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if (rtr)
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can_id |= 1 << MSCAN_EFF_RTR_SHIFT;
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out_be16(®s->tx.idr3_2, can_id);
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can_id >>= 16;
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/* EFF_FLAGS are between the IDs :( */
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can_id = (can_id & 0x7) | ((can_id << 2) & 0xffe0)
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| MSCAN_EFF_FLAGS;
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} else {
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can_id = (frame->can_id & CAN_SFF_MASK)
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<< (MSCAN_SFF_RTR_SHIFT + 1);
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if (rtr)
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can_id |= 1 << MSCAN_SFF_RTR_SHIFT;
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}
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out_be16(®s->tx.idr1_0, can_id);
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if (!rtr) {
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void __iomem *data = ®s->tx.dsr1_0;
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u16 *payload = (u16 *)frame->data;
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for (i = 0; i < frame->can_dlc / 2; i++) {
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out_be16(data, *payload++);
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data += 2 + _MSCAN_RESERVED_DSR_SIZE;
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}
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/* write remaining byte if necessary */
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if (frame->can_dlc & 1)
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out_8(data, frame->data[frame->can_dlc - 1]);
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}
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out_8(®s->tx.dlr, frame->can_dlc);
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out_8(®s->tx.tbpr, priv->cur_pri);
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/* Start transmission. */
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out_8(®s->cantflg, 1 << buf_id);
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if (!test_bit(F_TX_PROGRESS, &priv->flags))
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dev->trans_start = jiffies;
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list_add_tail(&priv->tx_queue[buf_id].list, &priv->tx_head);
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can_put_echo_skb(skb, dev, buf_id);
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/* Enable interrupt. */
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priv->tx_active |= 1 << buf_id;
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out_8(®s->cantier, priv->tx_active);
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return NETDEV_TX_OK;
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}
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/* This function returns the old state to see where we came from */
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static enum can_state check_set_state(struct net_device *dev, u8 canrflg)
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{
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struct mscan_priv *priv = netdev_priv(dev);
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enum can_state state, old_state = priv->can.state;
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if (canrflg & MSCAN_CSCIF && old_state <= CAN_STATE_BUS_OFF) {
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state = state_map[max(MSCAN_STATE_RX(canrflg),
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MSCAN_STATE_TX(canrflg))];
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priv->can.state = state;
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}
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return old_state;
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}
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static void mscan_get_rx_frame(struct net_device *dev, struct can_frame *frame)
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{
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struct mscan_priv *priv = netdev_priv(dev);
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struct mscan_regs __iomem *regs = priv->reg_base;
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u32 can_id;
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int i;
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can_id = in_be16(®s->rx.idr1_0);
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if (can_id & (1 << 3)) {
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frame->can_id = CAN_EFF_FLAG;
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can_id = ((can_id << 16) | in_be16(®s->rx.idr3_2));
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can_id = ((can_id & 0xffe00000) |
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((can_id & 0x7ffff) << 2)) >> 2;
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} else {
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can_id >>= 4;
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frame->can_id = 0;
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}
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frame->can_id |= can_id >> 1;
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if (can_id & 1)
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frame->can_id |= CAN_RTR_FLAG;
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frame->can_dlc = get_can_dlc(in_8(®s->rx.dlr) & 0xf);
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if (!(frame->can_id & CAN_RTR_FLAG)) {
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void __iomem *data = ®s->rx.dsr1_0;
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u16 *payload = (u16 *)frame->data;
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for (i = 0; i < frame->can_dlc / 2; i++) {
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*payload++ = in_be16(data);
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data += 2 + _MSCAN_RESERVED_DSR_SIZE;
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}
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/* read remaining byte if necessary */
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if (frame->can_dlc & 1)
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frame->data[frame->can_dlc - 1] = in_8(data);
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}
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out_8(®s->canrflg, MSCAN_RXF);
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}
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static void mscan_get_err_frame(struct net_device *dev, struct can_frame *frame,
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u8 canrflg)
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{
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struct mscan_priv *priv = netdev_priv(dev);
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struct mscan_regs __iomem *regs = priv->reg_base;
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struct net_device_stats *stats = &dev->stats;
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enum can_state old_state;
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netdev_dbg(dev, "error interrupt (canrflg=%#x)\n", canrflg);
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frame->can_id = CAN_ERR_FLAG;
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if (canrflg & MSCAN_OVRIF) {
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frame->can_id |= CAN_ERR_CRTL;
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frame->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
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stats->rx_over_errors++;
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stats->rx_errors++;
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} else {
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frame->data[1] = 0;
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}
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old_state = check_set_state(dev, canrflg);
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/* State changed */
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if (old_state != priv->can.state) {
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switch (priv->can.state) {
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case CAN_STATE_ERROR_WARNING:
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frame->can_id |= CAN_ERR_CRTL;
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priv->can.can_stats.error_warning++;
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if ((priv->shadow_statflg & MSCAN_RSTAT_MSK) <
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(canrflg & MSCAN_RSTAT_MSK))
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frame->data[1] |= CAN_ERR_CRTL_RX_WARNING;
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if ((priv->shadow_statflg & MSCAN_TSTAT_MSK) <
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(canrflg & MSCAN_TSTAT_MSK))
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frame->data[1] |= CAN_ERR_CRTL_TX_WARNING;
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break;
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case CAN_STATE_ERROR_PASSIVE:
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frame->can_id |= CAN_ERR_CRTL;
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priv->can.can_stats.error_passive++;
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frame->data[1] |= CAN_ERR_CRTL_RX_PASSIVE;
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break;
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case CAN_STATE_BUS_OFF:
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frame->can_id |= CAN_ERR_BUSOFF;
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/*
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* The MSCAN on the MPC5200 does recover from bus-off
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* automatically. To avoid that we stop the chip doing
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* a light-weight stop (we are in irq-context).
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*/
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if (priv->type != MSCAN_TYPE_MPC5121) {
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out_8(®s->cantier, 0);
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out_8(®s->canrier, 0);
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setbits8(®s->canctl0,
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MSCAN_SLPRQ | MSCAN_INITRQ);
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}
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can_bus_off(dev);
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break;
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default:
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break;
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}
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}
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priv->shadow_statflg = canrflg & MSCAN_STAT_MSK;
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frame->can_dlc = CAN_ERR_DLC;
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out_8(®s->canrflg, MSCAN_ERR_IF);
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}
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static int mscan_rx_poll(struct napi_struct *napi, int quota)
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{
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struct mscan_priv *priv = container_of(napi, struct mscan_priv, napi);
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struct net_device *dev = napi->dev;
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struct mscan_regs __iomem *regs = priv->reg_base;
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struct net_device_stats *stats = &dev->stats;
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int npackets = 0;
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int ret = 1;
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struct sk_buff *skb;
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struct can_frame *frame;
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u8 canrflg;
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while (npackets < quota) {
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canrflg = in_8(®s->canrflg);
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if (!(canrflg & (MSCAN_RXF | MSCAN_ERR_IF)))
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break;
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skb = alloc_can_skb(dev, &frame);
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if (!skb) {
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if (printk_ratelimit())
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netdev_notice(dev, "packet dropped\n");
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stats->rx_dropped++;
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out_8(®s->canrflg, canrflg);
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continue;
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}
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if (canrflg & MSCAN_RXF)
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mscan_get_rx_frame(dev, frame);
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else if (canrflg & MSCAN_ERR_IF)
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mscan_get_err_frame(dev, frame, canrflg);
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stats->rx_packets++;
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stats->rx_bytes += frame->can_dlc;
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npackets++;
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netif_receive_skb(skb);
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}
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if (!(in_8(®s->canrflg) & (MSCAN_RXF | MSCAN_ERR_IF))) {
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napi_complete(&priv->napi);
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clear_bit(F_RX_PROGRESS, &priv->flags);
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if (priv->can.state < CAN_STATE_BUS_OFF)
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out_8(®s->canrier, priv->shadow_canrier);
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ret = 0;
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}
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return ret;
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}
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|
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static irqreturn_t mscan_isr(int irq, void *dev_id)
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{
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struct net_device *dev = (struct net_device *)dev_id;
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|
struct mscan_priv *priv = netdev_priv(dev);
|
|
struct mscan_regs __iomem *regs = priv->reg_base;
|
|
struct net_device_stats *stats = &dev->stats;
|
|
u8 cantier, cantflg, canrflg;
|
|
irqreturn_t ret = IRQ_NONE;
|
|
|
|
cantier = in_8(®s->cantier) & MSCAN_TXE;
|
|
cantflg = in_8(®s->cantflg) & cantier;
|
|
|
|
if (cantier && cantflg) {
|
|
struct list_head *tmp, *pos;
|
|
|
|
list_for_each_safe(pos, tmp, &priv->tx_head) {
|
|
struct tx_queue_entry *entry =
|
|
list_entry(pos, struct tx_queue_entry, list);
|
|
u8 mask = entry->mask;
|
|
|
|
if (!(cantflg & mask))
|
|
continue;
|
|
|
|
out_8(®s->cantbsel, mask);
|
|
stats->tx_bytes += in_8(®s->tx.dlr);
|
|
stats->tx_packets++;
|
|
can_get_echo_skb(dev, entry->id);
|
|
priv->tx_active &= ~mask;
|
|
list_del(pos);
|
|
}
|
|
|
|
if (list_empty(&priv->tx_head)) {
|
|
clear_bit(F_TX_WAIT_ALL, &priv->flags);
|
|
clear_bit(F_TX_PROGRESS, &priv->flags);
|
|
priv->cur_pri = 0;
|
|
} else {
|
|
dev->trans_start = jiffies;
|
|
}
|
|
|
|
if (!test_bit(F_TX_WAIT_ALL, &priv->flags))
|
|
netif_wake_queue(dev);
|
|
|
|
out_8(®s->cantier, priv->tx_active);
|
|
ret = IRQ_HANDLED;
|
|
}
|
|
|
|
canrflg = in_8(®s->canrflg);
|
|
if ((canrflg & ~MSCAN_STAT_MSK) &&
|
|
!test_and_set_bit(F_RX_PROGRESS, &priv->flags)) {
|
|
if (canrflg & ~MSCAN_STAT_MSK) {
|
|
priv->shadow_canrier = in_8(®s->canrier);
|
|
out_8(®s->canrier, 0);
|
|
napi_schedule(&priv->napi);
|
|
ret = IRQ_HANDLED;
|
|
} else {
|
|
clear_bit(F_RX_PROGRESS, &priv->flags);
|
|
}
|
|
}
|
|
return ret;
|
|
}
|
|
|
|
static int mscan_do_set_mode(struct net_device *dev, enum can_mode mode)
|
|
{
|
|
struct mscan_priv *priv = netdev_priv(dev);
|
|
int ret = 0;
|
|
|
|
if (!priv->open_time)
|
|
return -EINVAL;
|
|
|
|
switch (mode) {
|
|
case CAN_MODE_START:
|
|
ret = mscan_restart(dev);
|
|
if (ret)
|
|
break;
|
|
if (netif_queue_stopped(dev))
|
|
netif_wake_queue(dev);
|
|
break;
|
|
|
|
default:
|
|
ret = -EOPNOTSUPP;
|
|
break;
|
|
}
|
|
return ret;
|
|
}
|
|
|
|
static int mscan_do_set_bittiming(struct net_device *dev)
|
|
{
|
|
struct mscan_priv *priv = netdev_priv(dev);
|
|
struct mscan_regs __iomem *regs = priv->reg_base;
|
|
struct can_bittiming *bt = &priv->can.bittiming;
|
|
u8 btr0, btr1;
|
|
|
|
btr0 = BTR0_SET_BRP(bt->brp) | BTR0_SET_SJW(bt->sjw);
|
|
btr1 = (BTR1_SET_TSEG1(bt->prop_seg + bt->phase_seg1) |
|
|
BTR1_SET_TSEG2(bt->phase_seg2) |
|
|
BTR1_SET_SAM(priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES));
|
|
|
|
netdev_info(dev, "setting BTR0=0x%02x BTR1=0x%02x\n", btr0, btr1);
|
|
|
|
out_8(®s->canbtr0, btr0);
|
|
out_8(®s->canbtr1, btr1);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int mscan_get_berr_counter(const struct net_device *dev,
|
|
struct can_berr_counter *bec)
|
|
{
|
|
struct mscan_priv *priv = netdev_priv(dev);
|
|
struct mscan_regs __iomem *regs = priv->reg_base;
|
|
|
|
bec->txerr = in_8(®s->cantxerr);
|
|
bec->rxerr = in_8(®s->canrxerr);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int mscan_open(struct net_device *dev)
|
|
{
|
|
int ret;
|
|
struct mscan_priv *priv = netdev_priv(dev);
|
|
struct mscan_regs __iomem *regs = priv->reg_base;
|
|
|
|
/* common open */
|
|
ret = open_candev(dev);
|
|
if (ret)
|
|
return ret;
|
|
|
|
napi_enable(&priv->napi);
|
|
|
|
ret = request_irq(dev->irq, mscan_isr, 0, dev->name, dev);
|
|
if (ret < 0) {
|
|
netdev_err(dev, "failed to attach interrupt\n");
|
|
goto exit_napi_disable;
|
|
}
|
|
|
|
priv->open_time = jiffies;
|
|
|
|
if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
|
|
setbits8(®s->canctl1, MSCAN_LISTEN);
|
|
else
|
|
clrbits8(®s->canctl1, MSCAN_LISTEN);
|
|
|
|
ret = mscan_start(dev);
|
|
if (ret)
|
|
goto exit_free_irq;
|
|
|
|
netif_start_queue(dev);
|
|
|
|
return 0;
|
|
|
|
exit_free_irq:
|
|
priv->open_time = 0;
|
|
free_irq(dev->irq, dev);
|
|
exit_napi_disable:
|
|
napi_disable(&priv->napi);
|
|
close_candev(dev);
|
|
return ret;
|
|
}
|
|
|
|
static int mscan_close(struct net_device *dev)
|
|
{
|
|
struct mscan_priv *priv = netdev_priv(dev);
|
|
struct mscan_regs __iomem *regs = priv->reg_base;
|
|
|
|
netif_stop_queue(dev);
|
|
napi_disable(&priv->napi);
|
|
|
|
out_8(®s->cantier, 0);
|
|
out_8(®s->canrier, 0);
|
|
mscan_set_mode(dev, MSCAN_INIT_MODE);
|
|
close_candev(dev);
|
|
free_irq(dev->irq, dev);
|
|
priv->open_time = 0;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct net_device_ops mscan_netdev_ops = {
|
|
.ndo_open = mscan_open,
|
|
.ndo_stop = mscan_close,
|
|
.ndo_start_xmit = mscan_start_xmit,
|
|
};
|
|
|
|
int register_mscandev(struct net_device *dev, int mscan_clksrc)
|
|
{
|
|
struct mscan_priv *priv = netdev_priv(dev);
|
|
struct mscan_regs __iomem *regs = priv->reg_base;
|
|
u8 ctl1;
|
|
|
|
ctl1 = in_8(®s->canctl1);
|
|
if (mscan_clksrc)
|
|
ctl1 |= MSCAN_CLKSRC;
|
|
else
|
|
ctl1 &= ~MSCAN_CLKSRC;
|
|
|
|
if (priv->type == MSCAN_TYPE_MPC5121) {
|
|
priv->can.do_get_berr_counter = mscan_get_berr_counter;
|
|
ctl1 |= MSCAN_BORM; /* bus-off recovery upon request */
|
|
}
|
|
|
|
ctl1 |= MSCAN_CANE;
|
|
out_8(®s->canctl1, ctl1);
|
|
udelay(100);
|
|
|
|
/* acceptance mask/acceptance code (accept everything) */
|
|
out_be16(®s->canidar1_0, 0);
|
|
out_be16(®s->canidar3_2, 0);
|
|
out_be16(®s->canidar5_4, 0);
|
|
out_be16(®s->canidar7_6, 0);
|
|
|
|
out_be16(®s->canidmr1_0, 0xffff);
|
|
out_be16(®s->canidmr3_2, 0xffff);
|
|
out_be16(®s->canidmr5_4, 0xffff);
|
|
out_be16(®s->canidmr7_6, 0xffff);
|
|
/* Two 32 bit Acceptance Filters */
|
|
out_8(®s->canidac, MSCAN_AF_32BIT);
|
|
|
|
mscan_set_mode(dev, MSCAN_INIT_MODE);
|
|
|
|
return register_candev(dev);
|
|
}
|
|
|
|
void unregister_mscandev(struct net_device *dev)
|
|
{
|
|
struct mscan_priv *priv = netdev_priv(dev);
|
|
struct mscan_regs __iomem *regs = priv->reg_base;
|
|
mscan_set_mode(dev, MSCAN_INIT_MODE);
|
|
clrbits8(®s->canctl1, MSCAN_CANE);
|
|
unregister_candev(dev);
|
|
}
|
|
|
|
struct net_device *alloc_mscandev(void)
|
|
{
|
|
struct net_device *dev;
|
|
struct mscan_priv *priv;
|
|
int i;
|
|
|
|
dev = alloc_candev(sizeof(struct mscan_priv), MSCAN_ECHO_SKB_MAX);
|
|
if (!dev)
|
|
return NULL;
|
|
priv = netdev_priv(dev);
|
|
|
|
dev->netdev_ops = &mscan_netdev_ops;
|
|
|
|
dev->flags |= IFF_ECHO; /* we support local echo */
|
|
|
|
netif_napi_add(dev, &priv->napi, mscan_rx_poll, 8);
|
|
|
|
priv->can.bittiming_const = &mscan_bittiming_const;
|
|
priv->can.do_set_bittiming = mscan_do_set_bittiming;
|
|
priv->can.do_set_mode = mscan_do_set_mode;
|
|
priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES |
|
|
CAN_CTRLMODE_LISTENONLY;
|
|
|
|
for (i = 0; i < TX_QUEUE_SIZE; i++) {
|
|
priv->tx_queue[i].id = i;
|
|
priv->tx_queue[i].mask = 1 << i;
|
|
}
|
|
|
|
return dev;
|
|
}
|
|
|
|
MODULE_AUTHOR("Andrey Volkov <avolkov@varma-el.com>");
|
|
MODULE_LICENSE("GPL v2");
|
|
MODULE_DESCRIPTION("CAN port driver for a MSCAN based chips");
|