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0e7b01aad2
This patch adds the missing SDHC devicetree nodes for i.MX27 SoCs. Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Acked-by: Sascha Hauer <s.hauer@pengutonix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
374 lines
8.6 KiB
Plaintext
374 lines
8.6 KiB
Plaintext
/*
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* Copyright 2012 Sascha Hauer, Pengutronix
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#include "skeleton.dtsi"
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/ {
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aliases {
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serial0 = &uart1;
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serial1 = &uart2;
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serial2 = &uart3;
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serial3 = &uart4;
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serial4 = &uart5;
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serial5 = &uart6;
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gpio0 = &gpio1;
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gpio1 = &gpio2;
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gpio2 = &gpio3;
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gpio3 = &gpio4;
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gpio4 = &gpio5;
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gpio5 = &gpio6;
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spi0 = &cspi1;
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spi1 = &cspi2;
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spi2 = &cspi3;
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};
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avic: avic-interrupt-controller@e0000000 {
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compatible = "fsl,imx27-avic", "fsl,avic";
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interrupt-controller;
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#interrupt-cells = <1>;
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reg = <0x10040000 0x1000>;
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};
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clocks {
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#address-cells = <1>;
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#size-cells = <0>;
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osc26m {
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compatible = "fsl,imx-osc26m", "fixed-clock";
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clock-frequency = <26000000>;
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};
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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interrupt-parent = <&avic>;
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ranges;
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aipi@10000000 { /* AIPI1 */
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compatible = "fsl,aipi-bus", "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x10000000 0x20000>;
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ranges;
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dma: dma@10001000 {
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compatible = "fsl,imx27-dma";
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reg = <0x10001000 0x1000>;
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interrupts = <32>;
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clocks = <&clks 50>, <&clks 70>;
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clock-names = "ipg", "ahb";
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#dma-cells = <1>;
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#dma-channels = <16>;
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};
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wdog: wdog@10002000 {
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compatible = "fsl,imx27-wdt", "fsl,imx21-wdt";
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reg = <0x10002000 0x1000>;
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interrupts = <27>;
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clocks = <&clks 0>;
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};
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gpt1: timer@10003000 {
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compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
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reg = <0x10003000 0x1000>;
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interrupts = <26>;
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clocks = <&clks 46>, <&clks 61>;
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clock-names = "ipg", "per";
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};
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gpt2: timer@10004000 {
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compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
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reg = <0x10004000 0x1000>;
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interrupts = <25>;
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clocks = <&clks 45>, <&clks 61>;
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clock-names = "ipg", "per";
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};
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gpt3: timer@10005000 {
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compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
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reg = <0x10005000 0x1000>;
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interrupts = <24>;
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clocks = <&clks 44>, <&clks 61>;
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clock-names = "ipg", "per";
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};
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pwm0: pwm@10006000 {
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compatible = "fsl,imx27-pwm";
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reg = <0x10006000 0x1000>;
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interrupts = <23>;
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clocks = <&clks 34>, <&clks 61>;
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clock-names = "ipg", "per";
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};
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uart1: serial@1000a000 {
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compatible = "fsl,imx27-uart", "fsl,imx21-uart";
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reg = <0x1000a000 0x1000>;
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interrupts = <20>;
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clocks = <&clks 81>, <&clks 61>;
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clock-names = "ipg", "per";
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status = "disabled";
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};
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uart2: serial@1000b000 {
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compatible = "fsl,imx27-uart", "fsl,imx21-uart";
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reg = <0x1000b000 0x1000>;
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interrupts = <19>;
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clocks = <&clks 80>, <&clks 61>;
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clock-names = "ipg", "per";
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status = "disabled";
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};
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uart3: serial@1000c000 {
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compatible = "fsl,imx27-uart", "fsl,imx21-uart";
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reg = <0x1000c000 0x1000>;
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interrupts = <18>;
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clocks = <&clks 79>, <&clks 61>;
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clock-names = "ipg", "per";
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status = "disabled";
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};
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uart4: serial@1000d000 {
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compatible = "fsl,imx27-uart", "fsl,imx21-uart";
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reg = <0x1000d000 0x1000>;
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interrupts = <17>;
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clocks = <&clks 78>, <&clks 61>;
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clock-names = "ipg", "per";
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status = "disabled";
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};
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cspi1: cspi@1000e000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx27-cspi";
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reg = <0x1000e000 0x1000>;
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interrupts = <16>;
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clocks = <&clks 53>, <&clks 53>;
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clock-names = "ipg", "per";
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status = "disabled";
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};
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cspi2: cspi@1000f000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx27-cspi";
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reg = <0x1000f000 0x1000>;
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interrupts = <15>;
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clocks = <&clks 52>, <&clks 52>;
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clock-names = "ipg", "per";
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status = "disabled";
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};
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i2c1: i2c@10012000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx27-i2c", "fsl,imx21-i2c";
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reg = <0x10012000 0x1000>;
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interrupts = <12>;
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clocks = <&clks 40>;
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status = "disabled";
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};
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sdhci1: sdhci@10013000 {
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compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
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reg = <0x10013000 0x1000>;
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interrupts = <11>;
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clocks = <&clks 30>, <&clks 60>;
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clock-names = "ipg", "per";
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dmas = <&dma 7>;
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dma-names = "rx-tx";
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status = "disabled";
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};
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sdhci2: sdhci@10014000 {
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compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
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reg = <0x10014000 0x1000>;
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interrupts = <10>;
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clocks = <&clks 29>, <&clks 60>;
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clock-names = "ipg", "per";
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dmas = <&dma 6>;
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dma-names = "rx-tx";
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status = "disabled";
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};
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gpio1: gpio@10015000 {
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compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
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reg = <0x10015000 0x100>;
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interrupts = <8>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio2: gpio@10015100 {
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compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
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reg = <0x10015100 0x100>;
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interrupts = <8>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio3: gpio@10015200 {
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compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
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reg = <0x10015200 0x100>;
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interrupts = <8>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio4: gpio@10015300 {
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compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
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reg = <0x10015300 0x100>;
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interrupts = <8>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio5: gpio@10015400 {
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compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
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reg = <0x10015400 0x100>;
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interrupts = <8>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio6: gpio@10015500 {
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compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
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reg = <0x10015500 0x100>;
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interrupts = <8>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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cspi3: cspi@10017000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx27-cspi";
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reg = <0x10017000 0x1000>;
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interrupts = <6>;
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clocks = <&clks 51>, <&clks 51>;
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clock-names = "ipg", "per";
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status = "disabled";
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};
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gpt4: timer@10019000 {
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compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
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reg = <0x10019000 0x1000>;
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interrupts = <4>;
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clocks = <&clks 43>, <&clks 61>;
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clock-names = "ipg", "per";
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};
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gpt5: timer@1001a000 {
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compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
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reg = <0x1001a000 0x1000>;
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interrupts = <3>;
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clocks = <&clks 42>, <&clks 61>;
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clock-names = "ipg", "per";
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};
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uart5: serial@1001b000 {
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compatible = "fsl,imx27-uart", "fsl,imx21-uart";
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reg = <0x1001b000 0x1000>;
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interrupts = <49>;
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clocks = <&clks 77>, <&clks 61>;
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clock-names = "ipg", "per";
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status = "disabled";
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};
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uart6: serial@1001c000 {
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compatible = "fsl,imx27-uart", "fsl,imx21-uart";
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reg = <0x1001c000 0x1000>;
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interrupts = <48>;
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clocks = <&clks 78>, <&clks 61>;
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clock-names = "ipg", "per";
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status = "disabled";
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};
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i2c2: i2c@1001d000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx27-i2c", "fsl,imx21-i2c";
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reg = <0x1001d000 0x1000>;
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interrupts = <1>;
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clocks = <&clks 39>;
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status = "disabled";
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};
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sdhci3: sdhci@1001e000 {
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compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
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reg = <0x1001e000 0x1000>;
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interrupts = <9>;
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clocks = <&clks 28>, <&clks 60>;
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clock-names = "ipg", "per";
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dmas = <&dma 36>;
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dma-names = "rx-tx";
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status = "disabled";
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};
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gpt6: timer@1001f000 {
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compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
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reg = <0x1001f000 0x1000>;
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interrupts = <2>;
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clocks = <&clks 41>, <&clks 61>;
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clock-names = "ipg", "per";
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};
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};
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aipi@10020000 { /* AIPI2 */
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compatible = "fsl,aipi-bus", "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x10020000 0x20000>;
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ranges;
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fec: ethernet@1002b000 {
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compatible = "fsl,imx27-fec";
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reg = <0x1002b000 0x4000>;
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interrupts = <50>;
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clocks = <&clks 48>, <&clks 67>, <&clks 0>;
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clock-names = "ipg", "ahb", "ptp";
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status = "disabled";
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};
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clks: ccm@10027000{
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compatible = "fsl,imx27-ccm";
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reg = <0x10027000 0x1000>;
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#clock-cells = <1>;
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};
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};
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nfc: nand@d8000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,imx27-nand";
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reg = <0xd8000000 0x1000>;
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interrupts = <29>;
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clocks = <&clks 54>;
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status = "disabled";
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};
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};
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};
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