Arnd Bergmann 0e7af99aef RISC-V soc fixes for v6.11-final ... StarFive: A fix to return one of the clocks on the JH7110 from 1 GHz to 1.5 GHz Signed-off-by: Conor Dooley <conor.dooley@microchip.com> -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCZt8G1wAKCRB4tDGHoIJi 0q/hAQD++rcYdOcP4iwguSS3ZkbCiyMdLDUuVvSiHUtR5dS0WgEAvXE1i0eEwt63 BELsrBNFkeUhLrBfHtN0k2MNvfPXxw4= =VjNw -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmbhWs4ACgkQYKtH/8kJ UieKcRAAyg582dYBmQr2z2u+X0XwR85nPCmwtZT7j1DbR+knBLt8s0+JqNu0g3sn NFg14CI3CtaTS96JaFOzXHKpD96oVTyozs0AU5jtCmD0/+RmOXIByrc1hMzRCP8C RNhFTwuuQsB3aP56EhL07CAwpTE0lZSdXORtQMn+vJ+H4RF5n0fzjujGLXWbEpOZ 8tmIFMEkgEILNcRxPRDLsa4hwUhqNiQDBNsV+QtDaaRfPUBHnXdfv88xkXZCX7EF wZRi+WobYbAIVIdEfQ01DfsjSKDmief3kZvm7nj4pBV0QP8O3sOe+xFrKcUguBwb 6tTACRzC9CaJvRNnkiHGvTMuT98500kd5P7TEnBZKgmHlWWYAxOivYO/mu/WYxVK Erb/i08XHopNK46xm1Ue/AM3eeXw6I6lAeZquEREZK2zGS6DE/LHTxHIlqelGEHt 9ubBlJLf6IVsmlzNrOyN7lrKkXhHqTkM5O8o3RCckTpsNrmV2TppjOl4s4FKWRPM o91f/FrS4CV8QdA7JQdmgB+pQWAE83txbTP5KAZpxEkTDBEd6b1NKllxXe3OD68y QA8B7lEw4ltxnzyD+WI4RIhYoBB+1IfguDy6CbtJ6gzKbmszfCXaxSCA1HpBbmPQ ilGFdrEFgT9NDbxHXOWsG/MHMjgOsi3e/h4XN/iYAjN0wwQ6ZSY= =1HB8 -----END PGP SIGNATURE----- Merge tag 'riscv-soc-fixes-for-v6.11-final' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into arm/fixes RISC-V soc fixes for v6.11-final StarFive: A fix to return one of the clocks on the JH7110 from 1 GHz to 1.5 GHz Signed-off-by: Conor Dooley <conor.dooley@microchip.com> * tag 'riscv-soc-fixes-for-v6.11-final' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux: riscv: dts: starfive: jh7110-common: Fix lower rate of CPUfreq by setting PLL0 rate to 1.5GHz Link: https://lore.kernel.org/r/20240909-hybrid-groovy-601a33b5b309@spud Signed-off-by: Arnd Bergmann <arnd@arndb.de>		2024-09-11 08:54:37 +00:00
..
boot	riscv: dts: starfive: jh7110-common: Fix lower rate of CPUfreq by setting PLL0 rate to 1.5GHz	2024-09-08 23:20:19 +01:00
configs	RISC-V: run savedefconfig for defconfig	2024-07-22 10:57:47 -07:00
crypto	crypto: riscv - add vector crypto accelerated AES-CBC-CTS	2024-03-20 08:56:11 -07:00
errata	riscv: Extend cpufeature.c to detect vendor extensions	2024-07-22 15:36:54 -07:00
include	RISC-V: hwprobe: Add SCALAR to misaligned perf defines	2024-08-14 13:13:24 -07:00
kernel	Merge patch series "RISC-V: hwprobe: Misaligned scalar perf fix and rename"	2024-08-15 13:12:21 -07:00
kvm	ARM:	2024-07-20 12:41:03 -07:00
lib	riscv: Optimize crc32 with Zbc extension	2024-07-10 13:19:50 -07:00
mm	riscv: change XIP's kernel_map.size to be size of the entire kernel	2024-08-14 13:12:33 -07:00
net	RISC-V Patches for the 6.11 Merge Window, Part 1	2024-07-20 09:11:27 -07:00
purgatory	riscv/purgatory: align riscv_kernel_entry	2024-08-01 07:14:34 -07:00
tools	riscv: Check relocations at compile time	2023-04-19 07:46:32 -07:00
Kbuild	RISC-V: hook new crypto subdir into build-system	2024-01-22 17:55:17 -08:00
Kconfig	RISC-V Patches for the 6.11 Merge Window, Part 2	2024-07-27 10:14:34 -07:00
Kconfig.debug	riscv: Add tests for riscv module loading	2023-11-07 14:59:32 -08:00
Kconfig.errata	riscv: thead: Rename T-Head PBMT to MAE	2024-04-25 10:22:33 -07:00
Kconfig.socs	RISC-V: drop SOC_VIRT for ARCH_VIRT	2024-04-10 11:37:50 +01:00
Kconfig.vendor	riscv: Extend cpufeature.c to detect vendor extensions	2024-07-22 15:36:54 -07:00
Makefile	Merge patch series "riscv: Apply Zawrs when available"	2024-07-12 08:55:29 -07:00
Makefile.postlink	kbuild: remove ARCH_POSTLINK from module builds	2023-10-28 21:10:08 +09:00