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0be267255c
When the watchdog device is suspended, its timeout is set to the maximum value. During resume, the previously set timeout should be restored. This does not work at the moment. The suspend function calls imx2_wdt_set_timeout(wdog, IMX2_WDT_MAX_TIME); and resume reverts this by calling imx2_wdt_set_timeout(wdog, wdog->timeout); However, imx2_wdt_set_timeout() updates wdog->timeout. Therefore, wdog->timeout is set to IMX2_WDT_MAX_TIME when we enter the resume function. Fix this by adding a new function __imx2_wdt_set_timeout() which only updates the hardware settings. imx2_wdt_set_timeout() now calls __imx2_wdt_set_timeout() and then saves the new timeout to wdog->timeout. During suspend, we call __imx2_wdt_set_timeout() directly so that wdog->timeout won't be updated and we can restore the previous value during resume. This approach makes wdog->timeout different from the actual setting in the hardware which is usually not a good thing. However, the two differ only while we're suspended and no kernel code is running, so it should be ok in this case. Signed-off-by: Martin Kaiser <martin@kaiser.cx> Cc: stable@vger.kernel.org Reviewed-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
446 lines
12 KiB
C
446 lines
12 KiB
C
/*
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* Watchdog driver for IMX2 and later processors
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*
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* Copyright (C) 2010 Wolfram Sang, Pengutronix e.K. <w.sang@pengutronix.de>
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* Copyright (C) 2014 Freescale Semiconductor, Inc.
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*
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* some parts adapted by similar drivers from Darius Augulis and Vladimir
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* Zapolskiy, additional improvements by Wim Van Sebroeck.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*
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* NOTE: MX1 has a slightly different Watchdog than MX2 and later:
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*
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* MX1: MX2+:
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* ---- -----
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* Registers: 32-bit 16-bit
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* Stopable timer: Yes No
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* Need to enable clk: No Yes
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* Halt on suspend: Manual Can be automatic
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/moduleparam.h>
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#include <linux/of_address.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/watchdog.h>
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#define DRIVER_NAME "imx2-wdt"
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#define IMX2_WDT_WCR 0x00 /* Control Register */
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#define IMX2_WDT_WCR_WT (0xFF << 8) /* -> Watchdog Timeout Field */
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#define IMX2_WDT_WCR_WDA BIT(5) /* -> External Reset WDOG_B */
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#define IMX2_WDT_WCR_SRS BIT(4) /* -> Software Reset Signal */
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#define IMX2_WDT_WCR_WRE BIT(3) /* -> WDOG Reset Enable */
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#define IMX2_WDT_WCR_WDE BIT(2) /* -> Watchdog Enable */
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#define IMX2_WDT_WCR_WDZST BIT(0) /* -> Watchdog timer Suspend */
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#define IMX2_WDT_WSR 0x02 /* Service Register */
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#define IMX2_WDT_SEQ1 0x5555 /* -> service sequence 1 */
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#define IMX2_WDT_SEQ2 0xAAAA /* -> service sequence 2 */
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#define IMX2_WDT_WRSR 0x04 /* Reset Status Register */
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#define IMX2_WDT_WRSR_TOUT BIT(1) /* -> Reset due to Timeout */
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#define IMX2_WDT_WICR 0x06 /* Interrupt Control Register */
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#define IMX2_WDT_WICR_WIE BIT(15) /* -> Interrupt Enable */
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#define IMX2_WDT_WICR_WTIS BIT(14) /* -> Interrupt Status */
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#define IMX2_WDT_WICR_WICT 0xFF /* -> Interrupt Count Timeout */
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#define IMX2_WDT_WMCR 0x08 /* Misc Register */
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#define IMX2_WDT_MAX_TIME 128
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#define IMX2_WDT_DEFAULT_TIME 60 /* in seconds */
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#define WDOG_SEC_TO_COUNT(s) ((s * 2 - 1) << 8)
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struct imx2_wdt_device {
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struct clk *clk;
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struct regmap *regmap;
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struct watchdog_device wdog;
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bool ext_reset;
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};
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static bool nowayout = WATCHDOG_NOWAYOUT;
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module_param(nowayout, bool, 0);
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MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
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__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
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static unsigned timeout = IMX2_WDT_DEFAULT_TIME;
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module_param(timeout, uint, 0);
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MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds (default="
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__MODULE_STRING(IMX2_WDT_DEFAULT_TIME) ")");
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static const struct watchdog_info imx2_wdt_info = {
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.identity = "imx2+ watchdog",
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.options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE,
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};
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static const struct watchdog_info imx2_wdt_pretimeout_info = {
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.identity = "imx2+ watchdog",
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.options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE |
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WDIOF_PRETIMEOUT,
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};
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static int imx2_wdt_restart(struct watchdog_device *wdog, unsigned long action,
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void *data)
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{
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struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
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unsigned int wcr_enable = IMX2_WDT_WCR_WDE;
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/* Use internal reset or external - not both */
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if (wdev->ext_reset)
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wcr_enable |= IMX2_WDT_WCR_SRS; /* do not assert int reset */
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else
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wcr_enable |= IMX2_WDT_WCR_WDA; /* do not assert ext-reset */
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/* Assert SRS signal */
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regmap_write(wdev->regmap, IMX2_WDT_WCR, wcr_enable);
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/*
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* Due to imx6q errata ERR004346 (WDOG: WDOG SRS bit requires to be
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* written twice), we add another two writes to ensure there must be at
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* least two writes happen in the same one 32kHz clock period. We save
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* the target check here, since the writes shouldn't be a huge burden
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* for other platforms.
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*/
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regmap_write(wdev->regmap, IMX2_WDT_WCR, wcr_enable);
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regmap_write(wdev->regmap, IMX2_WDT_WCR, wcr_enable);
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/* wait for reset to assert... */
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mdelay(500);
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return 0;
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}
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static inline void imx2_wdt_setup(struct watchdog_device *wdog)
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{
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struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
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u32 val;
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regmap_read(wdev->regmap, IMX2_WDT_WCR, &val);
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/* Suspend timer in low power mode, write once-only */
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val |= IMX2_WDT_WCR_WDZST;
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/* Strip the old watchdog Time-Out value */
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val &= ~IMX2_WDT_WCR_WT;
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/* Generate internal chip-level reset if WDOG times out */
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if (!wdev->ext_reset)
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val &= ~IMX2_WDT_WCR_WRE;
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/* Or if external-reset assert WDOG_B reset only on time-out */
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else
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val |= IMX2_WDT_WCR_WRE;
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/* Keep Watchdog Disabled */
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val &= ~IMX2_WDT_WCR_WDE;
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/* Set the watchdog's Time-Out value */
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val |= WDOG_SEC_TO_COUNT(wdog->timeout);
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regmap_write(wdev->regmap, IMX2_WDT_WCR, val);
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/* enable the watchdog */
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val |= IMX2_WDT_WCR_WDE;
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regmap_write(wdev->regmap, IMX2_WDT_WCR, val);
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}
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static inline bool imx2_wdt_is_running(struct imx2_wdt_device *wdev)
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{
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u32 val;
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regmap_read(wdev->regmap, IMX2_WDT_WCR, &val);
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return val & IMX2_WDT_WCR_WDE;
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}
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static int imx2_wdt_ping(struct watchdog_device *wdog)
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{
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struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
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regmap_write(wdev->regmap, IMX2_WDT_WSR, IMX2_WDT_SEQ1);
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regmap_write(wdev->regmap, IMX2_WDT_WSR, IMX2_WDT_SEQ2);
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return 0;
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}
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static void __imx2_wdt_set_timeout(struct watchdog_device *wdog,
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unsigned int new_timeout)
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{
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struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
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regmap_update_bits(wdev->regmap, IMX2_WDT_WCR, IMX2_WDT_WCR_WT,
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WDOG_SEC_TO_COUNT(new_timeout));
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}
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static int imx2_wdt_set_timeout(struct watchdog_device *wdog,
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unsigned int new_timeout)
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{
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__imx2_wdt_set_timeout(wdog, new_timeout);
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wdog->timeout = new_timeout;
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return 0;
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}
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static int imx2_wdt_set_pretimeout(struct watchdog_device *wdog,
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unsigned int new_pretimeout)
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{
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struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
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if (new_pretimeout >= IMX2_WDT_MAX_TIME)
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return -EINVAL;
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wdog->pretimeout = new_pretimeout;
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regmap_update_bits(wdev->regmap, IMX2_WDT_WICR,
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IMX2_WDT_WICR_WIE | IMX2_WDT_WICR_WICT,
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IMX2_WDT_WICR_WIE | (new_pretimeout << 1));
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return 0;
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}
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static irqreturn_t imx2_wdt_isr(int irq, void *wdog_arg)
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{
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struct watchdog_device *wdog = wdog_arg;
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struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
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regmap_write_bits(wdev->regmap, IMX2_WDT_WICR,
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IMX2_WDT_WICR_WTIS, IMX2_WDT_WICR_WTIS);
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watchdog_notify_pretimeout(wdog);
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return IRQ_HANDLED;
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}
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static int imx2_wdt_start(struct watchdog_device *wdog)
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{
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struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
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if (imx2_wdt_is_running(wdev))
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imx2_wdt_set_timeout(wdog, wdog->timeout);
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else
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imx2_wdt_setup(wdog);
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set_bit(WDOG_HW_RUNNING, &wdog->status);
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return imx2_wdt_ping(wdog);
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}
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static const struct watchdog_ops imx2_wdt_ops = {
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.owner = THIS_MODULE,
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.start = imx2_wdt_start,
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.ping = imx2_wdt_ping,
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.set_timeout = imx2_wdt_set_timeout,
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.set_pretimeout = imx2_wdt_set_pretimeout,
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.restart = imx2_wdt_restart,
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};
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static const struct regmap_config imx2_wdt_regmap_config = {
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.reg_bits = 16,
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.reg_stride = 2,
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.val_bits = 16,
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.max_register = 0x8,
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};
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static int __init imx2_wdt_probe(struct platform_device *pdev)
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{
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struct imx2_wdt_device *wdev;
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struct watchdog_device *wdog;
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struct resource *res;
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void __iomem *base;
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int ret;
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u32 val;
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wdev = devm_kzalloc(&pdev->dev, sizeof(*wdev), GFP_KERNEL);
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if (!wdev)
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return -ENOMEM;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(base))
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return PTR_ERR(base);
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wdev->regmap = devm_regmap_init_mmio_clk(&pdev->dev, NULL, base,
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&imx2_wdt_regmap_config);
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if (IS_ERR(wdev->regmap)) {
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dev_err(&pdev->dev, "regmap init failed\n");
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return PTR_ERR(wdev->regmap);
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}
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wdev->clk = devm_clk_get(&pdev->dev, NULL);
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if (IS_ERR(wdev->clk)) {
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dev_err(&pdev->dev, "can't get Watchdog clock\n");
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return PTR_ERR(wdev->clk);
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}
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wdog = &wdev->wdog;
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wdog->info = &imx2_wdt_info;
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wdog->ops = &imx2_wdt_ops;
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wdog->min_timeout = 1;
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wdog->max_hw_heartbeat_ms = IMX2_WDT_MAX_TIME * 1000;
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wdog->parent = &pdev->dev;
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ret = platform_get_irq(pdev, 0);
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if (ret > 0)
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if (!devm_request_irq(&pdev->dev, ret, imx2_wdt_isr, 0,
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dev_name(&pdev->dev), wdog))
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wdog->info = &imx2_wdt_pretimeout_info;
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ret = clk_prepare_enable(wdev->clk);
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if (ret)
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return ret;
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regmap_read(wdev->regmap, IMX2_WDT_WRSR, &val);
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wdog->bootstatus = val & IMX2_WDT_WRSR_TOUT ? WDIOF_CARDRESET : 0;
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wdev->ext_reset = of_property_read_bool(pdev->dev.of_node,
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"fsl,ext-reset-output");
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wdog->timeout = clamp_t(unsigned, timeout, 1, IMX2_WDT_MAX_TIME);
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if (wdog->timeout != timeout)
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dev_warn(&pdev->dev, "Initial timeout out of range! Clamped from %u to %u\n",
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timeout, wdog->timeout);
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platform_set_drvdata(pdev, wdog);
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watchdog_set_drvdata(wdog, wdev);
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watchdog_set_nowayout(wdog, nowayout);
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watchdog_set_restart_priority(wdog, 128);
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watchdog_init_timeout(wdog, timeout, &pdev->dev);
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if (imx2_wdt_is_running(wdev)) {
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imx2_wdt_set_timeout(wdog, wdog->timeout);
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set_bit(WDOG_HW_RUNNING, &wdog->status);
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}
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/*
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* Disable the watchdog power down counter at boot. Otherwise the power
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* down counter will pull down the #WDOG interrupt line for one clock
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* cycle.
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*/
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regmap_write(wdev->regmap, IMX2_WDT_WMCR, 0);
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ret = watchdog_register_device(wdog);
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if (ret) {
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dev_err(&pdev->dev, "cannot register watchdog device\n");
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goto disable_clk;
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}
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dev_info(&pdev->dev, "timeout %d sec (nowayout=%d)\n",
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wdog->timeout, nowayout);
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return 0;
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disable_clk:
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clk_disable_unprepare(wdev->clk);
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return ret;
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}
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static int __exit imx2_wdt_remove(struct platform_device *pdev)
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{
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struct watchdog_device *wdog = platform_get_drvdata(pdev);
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struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
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watchdog_unregister_device(wdog);
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if (imx2_wdt_is_running(wdev)) {
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imx2_wdt_ping(wdog);
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dev_crit(&pdev->dev, "Device removed: Expect reboot!\n");
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}
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return 0;
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}
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static void imx2_wdt_shutdown(struct platform_device *pdev)
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{
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struct watchdog_device *wdog = platform_get_drvdata(pdev);
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struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
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if (imx2_wdt_is_running(wdev)) {
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/*
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* We are running, configure max timeout before reboot
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* will take place.
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*/
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imx2_wdt_set_timeout(wdog, IMX2_WDT_MAX_TIME);
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imx2_wdt_ping(wdog);
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dev_crit(&pdev->dev, "Device shutdown: Expect reboot!\n");
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}
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}
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#ifdef CONFIG_PM_SLEEP
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/* Disable watchdog if it is active or non-active but still running */
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static int imx2_wdt_suspend(struct device *dev)
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{
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struct watchdog_device *wdog = dev_get_drvdata(dev);
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struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
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/* The watchdog IP block is running */
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if (imx2_wdt_is_running(wdev)) {
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/*
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* Don't update wdog->timeout, we'll restore the current value
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* during resume.
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*/
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__imx2_wdt_set_timeout(wdog, IMX2_WDT_MAX_TIME);
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imx2_wdt_ping(wdog);
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}
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clk_disable_unprepare(wdev->clk);
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return 0;
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}
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/* Enable watchdog and configure it if necessary */
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static int imx2_wdt_resume(struct device *dev)
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{
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struct watchdog_device *wdog = dev_get_drvdata(dev);
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struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
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int ret;
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ret = clk_prepare_enable(wdev->clk);
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if (ret)
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return ret;
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if (watchdog_active(wdog) && !imx2_wdt_is_running(wdev)) {
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/*
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* If the watchdog is still active and resumes
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* from deep sleep state, need to restart the
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* watchdog again.
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*/
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imx2_wdt_setup(wdog);
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}
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if (imx2_wdt_is_running(wdev)) {
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imx2_wdt_set_timeout(wdog, wdog->timeout);
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imx2_wdt_ping(wdog);
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}
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return 0;
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}
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#endif
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static SIMPLE_DEV_PM_OPS(imx2_wdt_pm_ops, imx2_wdt_suspend,
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imx2_wdt_resume);
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static const struct of_device_id imx2_wdt_dt_ids[] = {
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{ .compatible = "fsl,imx21-wdt", },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, imx2_wdt_dt_ids);
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static struct platform_driver imx2_wdt_driver = {
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.remove = __exit_p(imx2_wdt_remove),
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.shutdown = imx2_wdt_shutdown,
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.driver = {
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.name = DRIVER_NAME,
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.pm = &imx2_wdt_pm_ops,
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.of_match_table = imx2_wdt_dt_ids,
|
|
},
|
|
};
|
|
|
|
module_platform_driver_probe(imx2_wdt_driver, imx2_wdt_probe);
|
|
|
|
MODULE_AUTHOR("Wolfram Sang");
|
|
MODULE_DESCRIPTION("Watchdog driver for IMX2 and later");
|
|
MODULE_LICENSE("GPL v2");
|
|
MODULE_ALIAS("platform:" DRIVER_NAME);
|