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d5433fd60d
The Moxart does not appear to be using the interrupt from the watchdog timer, maybe it's not even routed, so as to support more architectures with this driver, make the interrupt optional. While we are at it: actually enable the use of the interrupt if present by setting the right bit in the control register and define the missing control register bits. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
237 lines
5.5 KiB
C
237 lines
5.5 KiB
C
/*
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* Watchdog driver for Faraday Technology FTWDT010
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*
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* Copyright (C) 2017 Linus Walleij <linus.walleij@linaro.org>
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*
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* Inspired by the out-of-tree drivers from OpenWRT:
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* Copyright (C) 2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/bitops.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/watchdog.h>
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#define FTWDT010_WDCOUNTER 0x0
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#define FTWDT010_WDLOAD 0x4
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#define FTWDT010_WDRESTART 0x8
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#define FTWDT010_WDCR 0xC
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#define WDRESTART_MAGIC 0x5AB9
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#define WDCR_CLOCK_5MHZ BIT(4)
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#define WDCR_WDEXT BIT(3)
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#define WDCR_WDINTR BIT(2)
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#define WDCR_SYS_RST BIT(1)
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#define WDCR_ENABLE BIT(0)
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#define WDT_CLOCK 5000000 /* 5 MHz */
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struct ftwdt010_wdt {
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struct watchdog_device wdd;
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struct device *dev;
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void __iomem *base;
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bool has_irq;
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};
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static inline
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struct ftwdt010_wdt *to_ftwdt010_wdt(struct watchdog_device *wdd)
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{
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return container_of(wdd, struct ftwdt010_wdt, wdd);
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}
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static int ftwdt010_wdt_start(struct watchdog_device *wdd)
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{
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struct ftwdt010_wdt *gwdt = to_ftwdt010_wdt(wdd);
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u32 enable;
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writel(wdd->timeout * WDT_CLOCK, gwdt->base + FTWDT010_WDLOAD);
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writel(WDRESTART_MAGIC, gwdt->base + FTWDT010_WDRESTART);
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/* set clock before enabling */
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enable = WDCR_CLOCK_5MHZ | WDCR_SYS_RST;
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writel(enable, gwdt->base + FTWDT010_WDCR);
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if (gwdt->has_irq)
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enable |= WDCR_WDINTR;
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enable |= WDCR_ENABLE;
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writel(enable, gwdt->base + FTWDT010_WDCR);
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return 0;
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}
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static int ftwdt010_wdt_stop(struct watchdog_device *wdd)
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{
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struct ftwdt010_wdt *gwdt = to_ftwdt010_wdt(wdd);
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writel(0, gwdt->base + FTWDT010_WDCR);
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return 0;
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}
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static int ftwdt010_wdt_ping(struct watchdog_device *wdd)
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{
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struct ftwdt010_wdt *gwdt = to_ftwdt010_wdt(wdd);
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writel(WDRESTART_MAGIC, gwdt->base + FTWDT010_WDRESTART);
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return 0;
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}
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static int ftwdt010_wdt_set_timeout(struct watchdog_device *wdd,
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unsigned int timeout)
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{
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wdd->timeout = timeout;
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if (watchdog_active(wdd))
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ftwdt010_wdt_start(wdd);
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return 0;
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}
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static irqreturn_t ftwdt010_wdt_interrupt(int irq, void *data)
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{
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struct ftwdt010_wdt *gwdt = data;
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watchdog_notify_pretimeout(&gwdt->wdd);
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return IRQ_HANDLED;
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}
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static const struct watchdog_ops ftwdt010_wdt_ops = {
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.start = ftwdt010_wdt_start,
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.stop = ftwdt010_wdt_stop,
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.ping = ftwdt010_wdt_ping,
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.set_timeout = ftwdt010_wdt_set_timeout,
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.owner = THIS_MODULE,
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};
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static const struct watchdog_info ftwdt010_wdt_info = {
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.options = WDIOF_KEEPALIVEPING
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| WDIOF_MAGICCLOSE
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| WDIOF_SETTIMEOUT,
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.identity = KBUILD_MODNAME,
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};
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static int ftwdt010_wdt_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct resource *res;
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struct ftwdt010_wdt *gwdt;
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unsigned int reg;
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int irq;
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int ret;
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gwdt = devm_kzalloc(dev, sizeof(*gwdt), GFP_KERNEL);
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if (!gwdt)
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return -ENOMEM;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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gwdt->base = devm_ioremap_resource(dev, res);
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if (IS_ERR(gwdt->base))
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return PTR_ERR(gwdt->base);
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gwdt->dev = dev;
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gwdt->wdd.info = &ftwdt010_wdt_info;
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gwdt->wdd.ops = &ftwdt010_wdt_ops;
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gwdt->wdd.min_timeout = 1;
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gwdt->wdd.max_timeout = 0xFFFFFFFF / WDT_CLOCK;
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gwdt->wdd.parent = dev;
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/*
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* If 'timeout-sec' unspecified in devicetree, assume a 13 second
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* default.
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*/
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gwdt->wdd.timeout = 13U;
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watchdog_init_timeout(&gwdt->wdd, 0, dev);
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reg = readw(gwdt->base + FTWDT010_WDCR);
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if (reg & WDCR_ENABLE) {
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/* Watchdog was enabled by the bootloader, disable it. */
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reg &= ~WDCR_ENABLE;
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writel(reg, gwdt->base + FTWDT010_WDCR);
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}
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irq = platform_get_irq(pdev, 0);
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if (irq) {
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ret = devm_request_irq(dev, irq, ftwdt010_wdt_interrupt, 0,
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"watchdog bark", gwdt);
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if (ret)
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return ret;
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gwdt->has_irq = true;
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}
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ret = devm_watchdog_register_device(dev, &gwdt->wdd);
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if (ret) {
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dev_err(&pdev->dev, "failed to register watchdog\n");
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return ret;
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}
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/* Set up platform driver data */
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platform_set_drvdata(pdev, gwdt);
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dev_info(dev, "FTWDT010 watchdog driver enabled\n");
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return 0;
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}
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static int __maybe_unused ftwdt010_wdt_suspend(struct device *dev)
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{
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struct ftwdt010_wdt *gwdt = dev_get_drvdata(dev);
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unsigned int reg;
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reg = readw(gwdt->base + FTWDT010_WDCR);
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reg &= ~WDCR_ENABLE;
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writel(reg, gwdt->base + FTWDT010_WDCR);
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return 0;
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}
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static int __maybe_unused ftwdt010_wdt_resume(struct device *dev)
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{
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struct ftwdt010_wdt *gwdt = dev_get_drvdata(dev);
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unsigned int reg;
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if (watchdog_active(&gwdt->wdd)) {
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reg = readw(gwdt->base + FTWDT010_WDCR);
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reg |= WDCR_ENABLE;
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writel(reg, gwdt->base + FTWDT010_WDCR);
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}
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return 0;
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}
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static const struct dev_pm_ops ftwdt010_wdt_dev_pm_ops = {
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SET_SYSTEM_SLEEP_PM_OPS(ftwdt010_wdt_suspend,
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ftwdt010_wdt_resume)
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};
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#ifdef CONFIG_OF
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static const struct of_device_id ftwdt010_wdt_match[] = {
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{ .compatible = "faraday,ftwdt010" },
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{ .compatible = "cortina,gemini-watchdog" },
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{},
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};
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MODULE_DEVICE_TABLE(of, ftwdt010_wdt_match);
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#endif
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static struct platform_driver ftwdt010_wdt_driver = {
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.probe = ftwdt010_wdt_probe,
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.driver = {
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.name = "ftwdt010-wdt",
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.of_match_table = of_match_ptr(ftwdt010_wdt_match),
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.pm = &ftwdt010_wdt_dev_pm_ops,
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},
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};
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module_platform_driver(ftwdt010_wdt_driver);
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MODULE_AUTHOR("Linus Walleij");
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MODULE_DESCRIPTION("Watchdog driver for Faraday Technology FTWDT010");
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MODULE_LICENSE("GPL");
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