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The R_INTC in the A31 and newer sun8i/sun50i SoCs is more similar to the
original sun4i interrupt controller than the sun7i/sun9i NMI controller.
It is used for two distinct purposes:
- To control the trigger, latch, and mask for the NMI input pin
- To provide the interrupt input for the ARISC coprocessor
As this interrupt controller is not documented, information about it
comes from vendor-provided firmware blobs and from experimentation.
Differences from the sun4i interrupt controller appear to be:
- It only has one or two registers of each kind (max 32 or 64 IRQs)
- Multiplexing logic is added to support additional inputs
- There is no FIQ-related logic
- There is no interrupt priority logic
In order to fulfill its two purposes, this hardware block combines four
types of IRQs. First, the NMI pin is routed to the "IRQ 0" input on this
chip, with a trigger type controlled by the NMI_CTRL_REG. The "IRQ 0
pending" output from this chip, if enabled, is then routed to a SPI IRQ
input on the GIC. In other words, bit 0 of IRQ_ENABLE_REG *does* affect
the NMI IRQ seen at the GIC.
The NMI is followed by a contiguous block of 15 "direct" (my name for
them) IRQ inputs that are connected in parallel to both R_INTC and the
GIC. Or in other words, these bits of IRQ_ENABLE_REG *do not* affect the
IRQs seen at the GIC.
Following the direct IRQs are the ARISC's copy of banked IRQs for shared
peripherals. These are not relevant to Linux. The remaining IRQs are
connected to a multiplexer and provide access to the first (up to) 128
SPIs from the ARISC. This range of SPIs overlaps with the direct IRQs.
Because of the 1:1 correspondence between R_INTC and GIC inputs, this is
a perfect scenario for using a stacked irqchip driver. We want to hook
into setting the NMI trigger type, but not actually handle any IRQ here.
To allow access to all multiplexed IRQs, this driver requires a new
binding where the interrupt number matches the GIC interrupt number.
(This moves the NMI from number 0 to 32 or 96, depending on the SoC.)
For simplicity, copy the three-cell GIC binding; this disambiguates
interrupt 0 in the old binding (the NMI) from interrupt 0 in the new
binding (SPI 0) by the number of cells.
Since R_INTC is in the always-on power domain, and its output is visible
to the power management coprocessor, a stacked irqchip driver provides a
simple way to add wakeup support to any of its IRQs. That is the next
patch; for now, just the NMI is moved over.
This commit mostly reverts commit 173bda53b3 ("irqchip/sunxi-nmi:
Support sun6i-a31-r-intc compatible").
Acked-by: Maxime Ripard <mripard@kernel.org>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20210118055040.21910-4-samuel@sholland.org
79 lines
1.5 KiB
Plaintext
79 lines
1.5 KiB
Plaintext
# SPDX-License-Identifier: GPL-2.0-only
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menuconfig ARCH_SUNXI
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bool "Allwinner SoCs"
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depends on ARCH_MULTI_V5 || ARCH_MULTI_V7
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select ARCH_HAS_RESET_CONTROLLER
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select CLKSRC_MMIO
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select GENERIC_IRQ_CHIP
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select GPIOLIB
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select IRQ_DOMAIN_HIERARCHY
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select IRQ_FASTEOI_HIERARCHY_HANDLERS
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select PINCTRL
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select PM_OPP
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select SUN4I_TIMER
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select RESET_CONTROLLER
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help
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Support for Allwinner ARM-based family of processors
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if ARCH_SUNXI
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if ARCH_MULTI_V7
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config MACH_SUN4I
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bool "Allwinner A10 (sun4i) SoCs support"
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default ARCH_SUNXI
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config MACH_SUN5I
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bool "Allwinner A10s / A13 (sun5i) SoCs support"
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default ARCH_SUNXI
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select SUN5I_HSTIMER
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config MACH_SUN6I
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bool "Allwinner A31 (sun6i) SoCs support"
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default ARCH_SUNXI
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select ARM_GIC
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select MFD_SUN6I_PRCM
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select SUN5I_HSTIMER
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config MACH_SUN7I
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bool "Allwinner A20 (sun7i) SoCs support"
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default ARCH_SUNXI
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select ARM_GIC
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select ARM_PSCI
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select ARCH_SUPPORTS_BIG_ENDIAN
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select HAVE_ARM_ARCH_TIMER
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select SUN5I_HSTIMER
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config MACH_SUN8I
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bool "Allwinner sun8i Family SoCs support"
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default ARCH_SUNXI
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select ARM_GIC
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select MFD_SUN6I_PRCM
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config MACH_SUN9I
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bool "Allwinner (sun9i) SoCs support"
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default ARCH_SUNXI
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select ARM_GIC
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config ARCH_SUNXI_MC_SMP
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bool
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depends on SMP
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default MACH_SUN9I || MACH_SUN8I
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select ARM_CCI400_PORT_CTRL
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select ARM_CPU_SUSPEND
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endif
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if ARCH_MULTI_V5
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config MACH_SUNIV
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bool "Allwinner ARMv5 F-series (suniv) SoCs support"
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default ARCH_SUNXI
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help
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Support for Allwinner suniv ARMv5 SoCs.
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(F1C100A, F1C100s, F1C200s, F1C500, F1C600)
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endif
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endif
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