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0daa55d033
CN10k SoCs use atomic stores of up to 128 bytes to submit packets/instructions into co-processor cores. The enqueueing is performed using Large Memory Transaction Store (LMTST) operations. They allow for lockless enqueue operations - i.e., two different CPU cores can submit instructions to the same queue without needing to lock the queue or synchronize their accesses. This patch implements a new debugfs entry for dumping LMTST map table present on CN10K, as this might be very useful to debug any issue in case of shared LMTST region among multiple pci functions. Signed-off-by: Harman Kalra <hkalra@marvell.com> Signed-off-by: Bhaskara Budiredla <bbudiredla@marvell.com> Signed-off-by: Rakesh Babu <rsaladi2@marvell.com> Signed-off-by: Sunil Kovvuri Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net> |
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| .. | ||
| mvpp2 | ||
| octeontx2 | ||
| prestera | ||
| Kconfig | ||
| Makefile | ||
| mv643xx_eth.c | ||
| mvmdio.c | ||
| mvneta_bm.c | ||
| mvneta_bm.h | ||
| mvneta.c | ||
| pxa168_eth.c | ||
| skge.c | ||
| skge.h | ||
| sky2.c | ||
| sky2.h | ||