Neil Armstrong 0d48fc558d clk: meson-gxbb: Add GXL/GXM GP0 Variant ... The clock tree in the Amlogic GXBB and GXL/GXM SoCs is shared, but the GXL/GXM SoCs embeds a different GP0 PLL, and needs different parameters with a vendor provided reduced rate table. This patch adds the GXL GP0 variant, and adds a GXL DT compatible in order to use the GXL GP0 PLL instead of the GXBB specific one. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/1490178747-14837-4-git-send-email-narmstrong@baylibre.com		2017-04-04 12:05:14 -07:00
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clk-cpu.c	clk: meson8b: clean up cpu clocks	2016-06-22 18:02:35 -07:00
clk-mpll.c	clk: meson: mpll: correct N2 maximum value	2017-03-27 12:30:38 -07:00
clk-pll.c	clk: meson: Add support for parameters for specific PLLs	2017-04-04 12:05:12 -07:00
clkc.h	clk: meson: Add support for parameters for specific PLLs	2017-04-04 12:05:12 -07:00
gxbb-aoclk.c	clk: meson: Fix invalid use of sizeof in gxbb_aoclkc_probe()	2016-08-24 00:55:13 -07:00
gxbb.c	clk: meson-gxbb: Add GXL/GXM GP0 Variant	2017-04-04 12:05:14 -07:00
gxbb.h	clk: meson-gxbb: Add GXL/GXM GP0 Variant	2017-04-04 12:05:14 -07:00
Kconfig	clk: gxbb: add AmLogic GXBB clk controller driver	2016-06-22 18:07:31 -07:00
Makefile	clk: meson: Rename meson8b-clkc.c to reflect gxbb naming convention	2016-09-01 17:31:44 -07:00
meson8b.c	clk: meson8b: add the mplls clocks 0, 1 and 2	2017-03-27 12:30:27 -07:00
meson8b.h	clk: meson8b: add the mplls clocks 0, 1 and 2	2017-03-27 12:30:27 -07:00