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27abe060aa
This patch adds an ath9k specific entry to read, write and reset the TSF into the debugfs, like in ath5k. This makes debugging the IBSS handling of wifi drivers _much_ easier. Signed-off-by: Alina Friedrichsen <x-alina@gmx.net> Signed-off-by: John W. Linville <linville@tuxdriver.com>
799 lines
22 KiB
C
799 lines
22 KiB
C
/*
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* Copyright (c) 2008 Atheros Communications Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef CORE_H
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#define CORE_H
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#include <linux/etherdevice.h>
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#include <linux/device.h>
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#include <net/mac80211.h>
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#include <linux/leds.h>
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#include <linux/rfkill.h>
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#include "ath9k.h"
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#include "rc.h"
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struct ath_node;
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/* Macro to expand scalars to 64-bit objects */
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#define ito64(x) (sizeof(x) == 8) ? \
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(((unsigned long long int)(x)) & (0xff)) : \
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(sizeof(x) == 16) ? \
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(((unsigned long long int)(x)) & 0xffff) : \
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((sizeof(x) == 32) ? \
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(((unsigned long long int)(x)) & 0xffffffff) : \
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(unsigned long long int)(x))
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/* increment with wrap-around */
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#define INCR(_l, _sz) do { \
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(_l)++; \
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(_l) &= ((_sz) - 1); \
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} while (0)
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/* decrement with wrap-around */
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#define DECR(_l, _sz) do { \
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(_l)--; \
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(_l) &= ((_sz) - 1); \
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} while (0)
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#define A_MAX(a, b) ((a) > (b) ? (a) : (b))
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#define ASSERT(exp) do { \
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if (unlikely(!(exp))) { \
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BUG(); \
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} \
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} while (0)
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#define TSF_TO_TU(_h,_l) \
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((((u32)(_h)) << 22) | (((u32)(_l)) >> 10))
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#define ATH_TXQ_SETUP(sc, i) ((sc)->tx.txqsetup & (1<<i))
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static const u8 ath_bcast_mac[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
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enum ATH_DEBUG {
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ATH_DBG_RESET = 0x00000001,
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ATH_DBG_REG_IO = 0x00000002,
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ATH_DBG_QUEUE = 0x00000004,
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ATH_DBG_EEPROM = 0x00000008,
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ATH_DBG_CALIBRATE = 0x00000010,
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ATH_DBG_CHANNEL = 0x00000020,
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ATH_DBG_INTERRUPT = 0x00000040,
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ATH_DBG_REGULATORY = 0x00000080,
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ATH_DBG_ANI = 0x00000100,
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ATH_DBG_POWER_MGMT = 0x00000200,
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ATH_DBG_XMIT = 0x00000400,
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ATH_DBG_BEACON = 0x00001000,
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ATH_DBG_CONFIG = 0x00002000,
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ATH_DBG_KEYCACHE = 0x00004000,
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ATH_DBG_FATAL = 0x00008000,
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ATH_DBG_ANY = 0xffffffff
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};
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#define DBG_DEFAULT (ATH_DBG_FATAL)
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#ifdef CONFIG_ATH9K_DEBUG
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/**
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* struct ath_interrupt_stats - Contains statistics about interrupts
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* @total: Total no. of interrupts generated so far
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* @rxok: RX with no errors
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* @rxeol: RX with no more RXDESC available
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* @rxorn: RX FIFO overrun
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* @txok: TX completed at the requested rate
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* @txurn: TX FIFO underrun
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* @mib: MIB regs reaching its threshold
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* @rxphyerr: RX with phy errors
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* @rx_keycache_miss: RX with key cache misses
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* @swba: Software Beacon Alert
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* @bmiss: Beacon Miss
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* @bnr: Beacon Not Ready
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* @cst: Carrier Sense TImeout
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* @gtt: Global TX Timeout
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* @tim: RX beacon TIM occurrence
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* @cabend: RX End of CAB traffic
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* @dtimsync: DTIM sync lossage
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* @dtim: RX Beacon with DTIM
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*/
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struct ath_interrupt_stats {
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u32 total;
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u32 rxok;
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u32 rxeol;
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u32 rxorn;
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u32 txok;
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u32 txeol;
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u32 txurn;
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u32 mib;
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u32 rxphyerr;
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u32 rx_keycache_miss;
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u32 swba;
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u32 bmiss;
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u32 bnr;
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u32 cst;
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u32 gtt;
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u32 tim;
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u32 cabend;
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u32 dtimsync;
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u32 dtim;
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};
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struct ath_stats {
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struct ath_interrupt_stats istats;
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};
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struct ath9k_debug {
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int debug_mask;
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struct dentry *debugfs_root;
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struct dentry *debugfs_phy;
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struct dentry *debugfs_dma;
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struct dentry *debugfs_interrupt;
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struct dentry *debugfs_tsf;
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struct ath_stats stats;
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};
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void DPRINTF(struct ath_softc *sc, int dbg_mask, const char *fmt, ...);
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int ath9k_init_debug(struct ath_softc *sc);
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void ath9k_exit_debug(struct ath_softc *sc);
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void ath_debug_stat_interrupt(struct ath_softc *sc, enum ath9k_int status);
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#else
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static inline void DPRINTF(struct ath_softc *sc, int dbg_mask,
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const char *fmt, ...)
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{
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}
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static inline int ath9k_init_debug(struct ath_softc *sc)
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{
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return 0;
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}
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static inline void ath9k_exit_debug(struct ath_softc *sc)
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{
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}
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static inline void ath_debug_stat_interrupt(struct ath_softc *sc,
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enum ath9k_int status)
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{
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}
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#endif /* CONFIG_ATH9K_DEBUG */
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struct ath_config {
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u32 ath_aggr_prot;
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u16 txpowlimit;
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u16 txpowlimit_override;
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u8 cabqReadytime;
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u8 swBeaconProcess;
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};
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/*************************/
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/* Descriptor Management */
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/*************************/
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#define ATH_TXBUF_RESET(_bf) do { \
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(_bf)->bf_status = 0; \
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(_bf)->bf_lastbf = NULL; \
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(_bf)->bf_next = NULL; \
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memset(&((_bf)->bf_state), 0, \
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sizeof(struct ath_buf_state)); \
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} while (0)
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enum buffer_type {
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BUF_DATA = BIT(0),
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BUF_AGGR = BIT(1),
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BUF_AMPDU = BIT(2),
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BUF_HT = BIT(3),
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BUF_RETRY = BIT(4),
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BUF_XRETRY = BIT(5),
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BUF_SHORT_PREAMBLE = BIT(6),
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BUF_BAR = BIT(7),
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BUF_PSPOLL = BIT(8),
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BUF_AGGR_BURST = BIT(9),
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BUF_CALC_AIRTIME = BIT(10),
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};
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struct ath_buf_state {
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int bfs_nframes; /* # frames in aggregate */
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u16 bfs_al; /* length of aggregate */
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u16 bfs_frmlen; /* length of frame */
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int bfs_seqno; /* sequence number */
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int bfs_tidno; /* tid of this frame */
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int bfs_retries; /* current retries */
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u32 bf_type; /* BUF_* (enum buffer_type) */
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u32 bfs_keyix;
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enum ath9k_key_type bfs_keytype;
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};
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#define bf_nframes bf_state.bfs_nframes
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#define bf_al bf_state.bfs_al
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#define bf_frmlen bf_state.bfs_frmlen
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#define bf_retries bf_state.bfs_retries
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#define bf_seqno bf_state.bfs_seqno
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#define bf_tidno bf_state.bfs_tidno
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#define bf_rcs bf_state.bfs_rcs
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#define bf_keyix bf_state.bfs_keyix
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#define bf_keytype bf_state.bfs_keytype
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#define bf_isdata(bf) (bf->bf_state.bf_type & BUF_DATA)
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#define bf_isaggr(bf) (bf->bf_state.bf_type & BUF_AGGR)
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#define bf_isampdu(bf) (bf->bf_state.bf_type & BUF_AMPDU)
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#define bf_isht(bf) (bf->bf_state.bf_type & BUF_HT)
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#define bf_isretried(bf) (bf->bf_state.bf_type & BUF_RETRY)
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#define bf_isxretried(bf) (bf->bf_state.bf_type & BUF_XRETRY)
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#define bf_isshpreamble(bf) (bf->bf_state.bf_type & BUF_SHORT_PREAMBLE)
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#define bf_isbar(bf) (bf->bf_state.bf_type & BUF_BAR)
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#define bf_ispspoll(bf) (bf->bf_state.bf_type & BUF_PSPOLL)
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#define bf_isaggrburst(bf) (bf->bf_state.bf_type & BUF_AGGR_BURST)
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/*
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* Abstraction of a contiguous buffer to transmit/receive. There is only
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* a single hw descriptor encapsulated here.
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*/
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struct ath_buf {
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struct list_head list;
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struct ath_buf *bf_lastbf; /* last buf of this unit (a frame or
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an aggregate) */
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struct ath_buf *bf_next; /* next subframe in the aggregate */
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void *bf_mpdu; /* enclosing frame structure */
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struct ath_desc *bf_desc; /* virtual addr of desc */
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dma_addr_t bf_daddr; /* physical addr of desc */
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dma_addr_t bf_buf_addr; /* physical addr of data buffer */
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u32 bf_status;
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u16 bf_flags; /* tx descriptor flags */
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struct ath_buf_state bf_state; /* buffer state */
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dma_addr_t bf_dmacontext;
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};
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#define ATH_RXBUF_RESET(_bf) ((_bf)->bf_status = 0)
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#define ATH_BUFSTATUS_STALE 0x00000002
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/* DMA state for tx/rx descriptors */
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struct ath_descdma {
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const char *dd_name;
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struct ath_desc *dd_desc; /* descriptors */
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dma_addr_t dd_desc_paddr; /* physical addr of dd_desc */
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u32 dd_desc_len; /* size of dd_desc */
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struct ath_buf *dd_bufptr; /* associated buffers */
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dma_addr_t dd_dmacontext;
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};
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int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
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struct list_head *head, const char *name,
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int nbuf, int ndesc);
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void ath_descdma_cleanup(struct ath_softc *sc, struct ath_descdma *dd,
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struct list_head *head);
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/***********/
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/* RX / TX */
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/***********/
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#define ATH_MAX_ANTENNA 3
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#define ATH_RXBUF 512
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#define WME_NUM_TID 16
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#define ATH_TXBUF 512
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#define ATH_TXMAXTRY 13
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#define ATH_11N_TXMAXTRY 10
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#define ATH_MGT_TXMAXTRY 4
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#define WME_BA_BMP_SIZE 64
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#define WME_MAX_BA WME_BA_BMP_SIZE
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#define ATH_TID_MAX_BUFS (2 * WME_MAX_BA)
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#define TID_TO_WME_AC(_tid) \
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((((_tid) == 0) || ((_tid) == 3)) ? WME_AC_BE : \
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(((_tid) == 1) || ((_tid) == 2)) ? WME_AC_BK : \
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(((_tid) == 4) || ((_tid) == 5)) ? WME_AC_VI : \
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WME_AC_VO)
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#define WME_AC_BE 0
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#define WME_AC_BK 1
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#define WME_AC_VI 2
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#define WME_AC_VO 3
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#define WME_NUM_AC 4
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#define ADDBA_EXCHANGE_ATTEMPTS 10
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#define ATH_AGGR_DELIM_SZ 4
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#define ATH_AGGR_MINPLEN 256 /* in bytes, minimum packet length */
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/* number of delimiters for encryption padding */
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#define ATH_AGGR_ENCRYPTDELIM 10
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/* minimum h/w qdepth to be sustained to maximize aggregation */
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#define ATH_AGGR_MIN_QDEPTH 2
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#define ATH_AMPDU_SUBFRAME_DEFAULT 32
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#define IEEE80211_SEQ_SEQ_SHIFT 4
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#define IEEE80211_SEQ_MAX 4096
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#define IEEE80211_MIN_AMPDU_BUF 0x8
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#define IEEE80211_HTCAP_MAXRXAMPDU_FACTOR 13
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/* return whether a bit at index _n in bitmap _bm is set
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* _sz is the size of the bitmap */
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#define ATH_BA_ISSET(_bm, _n) (((_n) < (WME_BA_BMP_SIZE)) && \
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((_bm)[(_n) >> 5] & (1 << ((_n) & 31))))
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/* return block-ack bitmap index given sequence and starting sequence */
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#define ATH_BA_INDEX(_st, _seq) (((_seq) - (_st)) & (IEEE80211_SEQ_MAX - 1))
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/* returns delimiter padding required given the packet length */
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#define ATH_AGGR_GET_NDELIM(_len) \
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(((((_len) + ATH_AGGR_DELIM_SZ) < ATH_AGGR_MINPLEN) ? \
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(ATH_AGGR_MINPLEN - (_len) - ATH_AGGR_DELIM_SZ) : 0) >> 2)
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#define BAW_WITHIN(_start, _bawsz, _seqno) \
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((((_seqno) - (_start)) & 4095) < (_bawsz))
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#define ATH_DS_BA_SEQ(_ds) ((_ds)->ds_us.tx.ts_seqnum)
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#define ATH_DS_BA_BITMAP(_ds) (&(_ds)->ds_us.tx.ba_low)
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#define ATH_DS_TX_BA(_ds) ((_ds)->ds_us.tx.ts_flags & ATH9K_TX_BA)
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#define ATH_AN_2_TID(_an, _tidno) (&(_an)->tid[(_tidno)])
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enum ATH_AGGR_STATUS {
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ATH_AGGR_DONE,
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ATH_AGGR_BAW_CLOSED,
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ATH_AGGR_LIMITED,
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ATH_AGGR_SHORTPKT,
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ATH_AGGR_8K_LIMITED,
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};
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struct ath_txq {
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u32 axq_qnum; /* hardware q number */
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u32 *axq_link; /* link ptr in last TX desc */
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struct list_head axq_q; /* transmit queue */
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spinlock_t axq_lock;
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u32 axq_depth; /* queue depth */
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u8 axq_aggr_depth; /* aggregates queued */
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u32 axq_totalqueued; /* total ever queued */
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bool stopped; /* Is mac80211 queue stopped ? */
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struct ath_buf *axq_linkbuf; /* virtual addr of last buffer*/
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/* first desc of the last descriptor that contains CTS */
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struct ath_desc *axq_lastdsWithCTS;
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/* final desc of the gating desc that determines whether
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lastdsWithCTS has been DMA'ed or not */
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struct ath_desc *axq_gatingds;
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struct list_head axq_acq;
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};
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#define AGGR_CLEANUP BIT(1)
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#define AGGR_ADDBA_COMPLETE BIT(2)
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#define AGGR_ADDBA_PROGRESS BIT(3)
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/* per TID aggregate tx state for a destination */
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struct ath_atx_tid {
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struct list_head list; /* round-robin tid entry */
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struct list_head buf_q; /* pending buffers */
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struct ath_node *an;
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struct ath_atx_ac *ac;
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struct ath_buf *tx_buf[ATH_TID_MAX_BUFS]; /* active tx frames */
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u16 seq_start;
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u16 seq_next;
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u16 baw_size;
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int tidno;
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int baw_head; /* first un-acked tx buffer */
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int baw_tail; /* next unused tx buffer slot */
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int sched;
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int paused;
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u8 state;
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int addba_exchangeattempts;
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};
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/* per access-category aggregate tx state for a destination */
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struct ath_atx_ac {
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int sched; /* dest-ac is scheduled */
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int qnum; /* H/W queue number associated
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with this AC */
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struct list_head list; /* round-robin txq entry */
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struct list_head tid_q; /* queue of TIDs with buffers */
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};
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/* per-frame tx control block */
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struct ath_tx_control {
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struct ath_txq *txq;
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int if_id;
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};
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/* per frame tx status block */
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struct ath_xmit_status {
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int retries; /* number of retries to successufully
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transmit this frame */
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int flags; /* status of transmit */
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#define ATH_TX_ERROR 0x01
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#define ATH_TX_XRETRY 0x02
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#define ATH_TX_BAR 0x04
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};
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/* All RSSI values are noise floor adjusted */
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struct ath_tx_stat {
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int rssi;
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int rssictl[ATH_MAX_ANTENNA];
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int rssiextn[ATH_MAX_ANTENNA];
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int rateieee;
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int rateKbps;
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int ratecode;
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int flags;
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u32 airtime; /* time on air per final tx rate */
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};
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struct aggr_rifs_param {
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int param_max_frames;
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int param_max_len;
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int param_rl;
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int param_al;
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struct ath_rc_series *param_rcs;
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};
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struct ath_node {
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struct ath_softc *an_sc;
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struct ath_atx_tid tid[WME_NUM_TID];
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struct ath_atx_ac ac[WME_NUM_AC];
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u16 maxampdu;
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u8 mpdudensity;
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};
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struct ath_tx {
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u16 seq_no;
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u32 txqsetup;
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int hwq_map[ATH9K_WME_AC_VO+1];
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spinlock_t txbuflock;
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struct list_head txbuf;
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struct ath_txq txq[ATH9K_NUM_TX_QUEUES];
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struct ath_descdma txdma;
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};
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struct ath_rx {
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u8 defant;
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u8 rxotherant;
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u32 *rxlink;
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int bufsize;
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unsigned int rxfilter;
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spinlock_t rxflushlock;
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spinlock_t rxbuflock;
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struct list_head rxbuf;
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struct ath_descdma rxdma;
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};
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int ath_startrecv(struct ath_softc *sc);
|
|
bool ath_stoprecv(struct ath_softc *sc);
|
|
void ath_flushrecv(struct ath_softc *sc);
|
|
u32 ath_calcrxfilter(struct ath_softc *sc);
|
|
int ath_rx_init(struct ath_softc *sc, int nbufs);
|
|
void ath_rx_cleanup(struct ath_softc *sc);
|
|
int ath_rx_tasklet(struct ath_softc *sc, int flush);
|
|
struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype);
|
|
void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq);
|
|
int ath_tx_setup(struct ath_softc *sc, int haltype);
|
|
void ath_drain_all_txq(struct ath_softc *sc, bool retry_tx);
|
|
void ath_draintxq(struct ath_softc *sc,
|
|
struct ath_txq *txq, bool retry_tx);
|
|
void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an);
|
|
void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an);
|
|
void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq);
|
|
int ath_tx_init(struct ath_softc *sc, int nbufs);
|
|
int ath_tx_cleanup(struct ath_softc *sc);
|
|
struct ath_txq *ath_test_get_txq(struct ath_softc *sc, struct sk_buff *skb);
|
|
int ath_txq_update(struct ath_softc *sc, int qnum,
|
|
struct ath9k_tx_queue_info *q);
|
|
int ath_tx_start(struct ath_softc *sc, struct sk_buff *skb,
|
|
struct ath_tx_control *txctl);
|
|
void ath_tx_tasklet(struct ath_softc *sc);
|
|
void ath_tx_cabq(struct ath_softc *sc, struct sk_buff *skb);
|
|
bool ath_tx_aggr_check(struct ath_softc *sc, struct ath_node *an, u8 tidno);
|
|
int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
|
|
u16 tid, u16 *ssn);
|
|
int ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
|
|
void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
|
|
|
|
/********/
|
|
/* VAPs */
|
|
/********/
|
|
|
|
/*
|
|
* Define the scheme that we select MAC address for multiple
|
|
* BSS on the same radio. The very first VAP will just use the MAC
|
|
* address from the EEPROM. For the next 3 VAPs, we set the
|
|
* U/L bit (bit 1) in MAC address, and use the next two bits as the
|
|
* index of the VAP.
|
|
*/
|
|
|
|
#define ATH_SET_VAP_BSSID_MASK(bssid_mask) \
|
|
((bssid_mask)[0] &= ~(((ATH_BCBUF-1)<<2)|0x02))
|
|
|
|
struct ath_vap {
|
|
int av_bslot;
|
|
enum nl80211_iftype av_opmode;
|
|
struct ath_buf *av_bcbuf;
|
|
struct ath_tx_control av_btxctl;
|
|
};
|
|
|
|
/*******************/
|
|
/* Beacon Handling */
|
|
/*******************/
|
|
|
|
/*
|
|
* Regardless of the number of beacons we stagger, (i.e. regardless of the
|
|
* number of BSSIDs) if a given beacon does not go out even after waiting this
|
|
* number of beacon intervals, the game's up.
|
|
*/
|
|
#define BSTUCK_THRESH (9 * ATH_BCBUF)
|
|
#define ATH_BCBUF 1
|
|
#define ATH_DEFAULT_BINTVAL 100 /* TU */
|
|
#define ATH_DEFAULT_BMISS_LIMIT 10
|
|
#define IEEE80211_MS_TO_TU(x) (((x) * 1000) / 1024)
|
|
|
|
struct ath_beacon_config {
|
|
u16 beacon_interval;
|
|
u16 listen_interval;
|
|
u16 dtim_period;
|
|
u16 bmiss_timeout;
|
|
u8 dtim_count;
|
|
u8 tim_offset;
|
|
union {
|
|
u64 last_tsf;
|
|
u8 last_tstamp[8];
|
|
} u; /* last received beacon/probe response timestamp of this BSS. */
|
|
};
|
|
|
|
struct ath_beacon {
|
|
enum {
|
|
OK, /* no change needed */
|
|
UPDATE, /* update pending */
|
|
COMMIT /* beacon sent, commit change */
|
|
} updateslot; /* slot time update fsm */
|
|
|
|
u32 beaconq;
|
|
u32 bmisscnt;
|
|
u32 ast_be_xmit;
|
|
u64 bc_tstamp;
|
|
int bslot[ATH_BCBUF];
|
|
int slottime;
|
|
int slotupdate;
|
|
struct ath9k_tx_queue_info beacon_qi;
|
|
struct ath_descdma bdma;
|
|
struct ath_txq *cabq;
|
|
struct list_head bbuf;
|
|
};
|
|
|
|
void ath9k_beacon_tasklet(unsigned long data);
|
|
void ath_beacon_config(struct ath_softc *sc, int if_id);
|
|
int ath_beaconq_setup(struct ath_hal *ah);
|
|
int ath_beacon_alloc(struct ath_softc *sc, int if_id);
|
|
void ath_beacon_return(struct ath_softc *sc, struct ath_vap *avp);
|
|
void ath_beacon_sync(struct ath_softc *sc, int if_id);
|
|
|
|
/*******/
|
|
/* ANI */
|
|
/*******/
|
|
|
|
/* ANI values for STA only.
|
|
FIXME: Add appropriate values for AP later */
|
|
|
|
#define ATH_ANI_POLLINTERVAL 100 /* 100 milliseconds between ANI poll */
|
|
#define ATH_SHORT_CALINTERVAL 1000 /* 1 second between calibrations */
|
|
#define ATH_LONG_CALINTERVAL 30000 /* 30 seconds between calibrations */
|
|
#define ATH_RESTART_CALINTERVAL 1200000 /* 20 minutes between calibrations */
|
|
|
|
struct ath_ani {
|
|
bool sc_caldone;
|
|
int16_t sc_noise_floor;
|
|
unsigned int sc_longcal_timer;
|
|
unsigned int sc_shortcal_timer;
|
|
unsigned int sc_resetcal_timer;
|
|
unsigned int sc_checkani_timer;
|
|
struct timer_list timer;
|
|
};
|
|
|
|
/********************/
|
|
/* LED Control */
|
|
/********************/
|
|
|
|
#define ATH_LED_PIN 1
|
|
|
|
enum ath_led_type {
|
|
ATH_LED_RADIO,
|
|
ATH_LED_ASSOC,
|
|
ATH_LED_TX,
|
|
ATH_LED_RX
|
|
};
|
|
|
|
struct ath_led {
|
|
struct ath_softc *sc;
|
|
struct led_classdev led_cdev;
|
|
enum ath_led_type led_type;
|
|
char name[32];
|
|
bool registered;
|
|
};
|
|
|
|
/* Rfkill */
|
|
#define ATH_RFKILL_POLL_INTERVAL 2000 /* msecs */
|
|
|
|
struct ath_rfkill {
|
|
struct rfkill *rfkill;
|
|
struct delayed_work rfkill_poll;
|
|
char rfkill_name[32];
|
|
};
|
|
|
|
/********************/
|
|
/* Main driver core */
|
|
/********************/
|
|
|
|
/*
|
|
* Default cache line size, in bytes.
|
|
* Used when PCI device not fully initialized by bootrom/BIOS
|
|
*/
|
|
#define DEFAULT_CACHELINE 32
|
|
#define ATH_DEFAULT_NOISE_FLOOR -95
|
|
#define ATH_REGCLASSIDS_MAX 10
|
|
#define ATH_CABQ_READY_TIME 80 /* % of beacon interval */
|
|
#define ATH_MAX_SW_RETRIES 10
|
|
#define ATH_CHAN_MAX 255
|
|
#define IEEE80211_WEP_NKID 4 /* number of key ids */
|
|
#define IEEE80211_RATE_VAL 0x7f
|
|
/*
|
|
* The key cache is used for h/w cipher state and also for
|
|
* tracking station state such as the current tx antenna.
|
|
* We also setup a mapping table between key cache slot indices
|
|
* and station state to short-circuit node lookups on rx.
|
|
* Different parts have different size key caches. We handle
|
|
* up to ATH_KEYMAX entries (could dynamically allocate state).
|
|
*/
|
|
#define ATH_KEYMAX 128 /* max key cache size we handle */
|
|
|
|
#define ATH_IF_ID_ANY 0xff
|
|
#define ATH_TXPOWER_MAX 100 /* .5 dBm units */
|
|
#define ATH_RSSI_DUMMY_MARKER 0x127
|
|
#define ATH_RATE_DUMMY_MARKER 0
|
|
|
|
enum PROT_MODE {
|
|
PROT_M_NONE = 0,
|
|
PROT_M_RTSCTS,
|
|
PROT_M_CTSONLY
|
|
};
|
|
|
|
#define SC_OP_INVALID BIT(0)
|
|
#define SC_OP_BEACONS BIT(1)
|
|
#define SC_OP_RXAGGR BIT(2)
|
|
#define SC_OP_TXAGGR BIT(3)
|
|
#define SC_OP_CHAINMASK_UPDATE BIT(4)
|
|
#define SC_OP_FULL_RESET BIT(5)
|
|
#define SC_OP_NO_RESET BIT(6)
|
|
#define SC_OP_PREAMBLE_SHORT BIT(7)
|
|
#define SC_OP_PROTECT_ENABLE BIT(8)
|
|
#define SC_OP_RXFLUSH BIT(9)
|
|
#define SC_OP_LED_ASSOCIATED BIT(10)
|
|
#define SC_OP_RFKILL_REGISTERED BIT(11)
|
|
#define SC_OP_RFKILL_SW_BLOCKED BIT(12)
|
|
#define SC_OP_RFKILL_HW_BLOCKED BIT(13)
|
|
#define SC_OP_WAIT_FOR_BEACON BIT(14)
|
|
|
|
struct ath_bus_ops {
|
|
void (*read_cachesize)(struct ath_softc *sc, int *csz);
|
|
void (*cleanup)(struct ath_softc *sc);
|
|
bool (*eeprom_read)(struct ath_hal *ah, u32 off, u16 *data);
|
|
};
|
|
|
|
struct ath_softc {
|
|
struct ieee80211_hw *hw;
|
|
struct device *dev;
|
|
struct tasklet_struct intr_tq;
|
|
struct tasklet_struct bcon_tasklet;
|
|
struct ath_hal *sc_ah;
|
|
void __iomem *mem;
|
|
int irq;
|
|
spinlock_t sc_resetlock;
|
|
struct mutex mutex;
|
|
|
|
u8 sc_curbssid[ETH_ALEN];
|
|
u8 sc_myaddr[ETH_ALEN];
|
|
u8 sc_bssidmask[ETH_ALEN];
|
|
u32 sc_intrstatus;
|
|
u32 sc_flags; /* SC_OP_* */
|
|
u16 sc_curtxpow;
|
|
u16 sc_curaid;
|
|
u16 sc_cachelsz;
|
|
u8 sc_nbcnvaps;
|
|
u16 sc_nvaps;
|
|
u8 sc_tx_chainmask;
|
|
u8 sc_rx_chainmask;
|
|
u32 sc_keymax;
|
|
DECLARE_BITMAP(sc_keymap, ATH_KEYMAX);
|
|
u8 sc_splitmic;
|
|
atomic_t ps_usecount;
|
|
enum ath9k_int sc_imask;
|
|
enum PROT_MODE sc_protmode;
|
|
enum ath9k_ht_extprotspacing sc_ht_extprotspacing;
|
|
enum ath9k_ht_macmode tx_chan_width;
|
|
|
|
struct ath_config sc_config;
|
|
struct ath_rx rx;
|
|
struct ath_tx tx;
|
|
struct ath_beacon beacon;
|
|
struct ieee80211_vif *sc_vaps[ATH_BCBUF];
|
|
struct ieee80211_rate rates[IEEE80211_NUM_BANDS][ATH_RATE_MAX];
|
|
struct ath_rate_table *hw_rate_table[ATH9K_MODE_MAX];
|
|
struct ath_rate_table *cur_rate_table;
|
|
struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
|
|
struct ath_led radio_led;
|
|
struct ath_led assoc_led;
|
|
struct ath_led tx_led;
|
|
struct ath_led rx_led;
|
|
struct ath_rfkill rf_kill;
|
|
struct ath_ani sc_ani;
|
|
struct ath9k_node_stats sc_halstats;
|
|
#ifdef CONFIG_ATH9K_DEBUG
|
|
struct ath9k_debug sc_debug;
|
|
#endif
|
|
struct ath_bus_ops *bus_ops;
|
|
};
|
|
|
|
int ath_reset(struct ath_softc *sc, bool retry_tx);
|
|
int ath_get_hal_qnum(u16 queue, struct ath_softc *sc);
|
|
int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc);
|
|
int ath_cabq_update(struct ath_softc *);
|
|
|
|
static inline void ath_read_cachesize(struct ath_softc *sc, int *csz)
|
|
{
|
|
sc->bus_ops->read_cachesize(sc, csz);
|
|
}
|
|
|
|
static inline void ath_bus_cleanup(struct ath_softc *sc)
|
|
{
|
|
sc->bus_ops->cleanup(sc);
|
|
}
|
|
|
|
extern struct ieee80211_ops ath9k_ops;
|
|
|
|
irqreturn_t ath_isr(int irq, void *dev);
|
|
void ath_cleanup(struct ath_softc *sc);
|
|
int ath_attach(u16 devid, struct ath_softc *sc);
|
|
void ath_detach(struct ath_softc *sc);
|
|
const char *ath_mac_bb_name(u32 mac_bb_version);
|
|
const char *ath_rf_name(u16 rf_version);
|
|
|
|
#ifdef CONFIG_PCI
|
|
int ath_pci_init(void);
|
|
void ath_pci_exit(void);
|
|
#else
|
|
static inline int ath_pci_init(void) { return 0; };
|
|
static inline void ath_pci_exit(void) {};
|
|
#endif
|
|
|
|
#ifdef CONFIG_ATHEROS_AR71XX
|
|
int ath_ahb_init(void);
|
|
void ath_ahb_exit(void);
|
|
#else
|
|
static inline int ath_ahb_init(void) { return 0; };
|
|
static inline void ath_ahb_exit(void) {};
|
|
#endif
|
|
|
|
static inline void ath9k_ps_wakeup(struct ath_softc *sc)
|
|
{
|
|
if (atomic_inc_return(&sc->ps_usecount) == 1)
|
|
if (sc->sc_ah->ah_power_mode != ATH9K_PM_AWAKE) {
|
|
sc->sc_ah->ah_restore_mode = sc->sc_ah->ah_power_mode;
|
|
ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
|
|
}
|
|
}
|
|
|
|
static inline void ath9k_ps_restore(struct ath_softc *sc)
|
|
{
|
|
if (atomic_dec_and_test(&sc->ps_usecount))
|
|
if (sc->hw->conf.flags & IEEE80211_CONF_PS)
|
|
ath9k_hw_setpower(sc->sc_ah,
|
|
sc->sc_ah->ah_restore_mode);
|
|
}
|
|
#endif /* CORE_H */
|