Linus Torvalds 23221d997b arm64 updates for 4.17 ... Nothing particularly stands out here, probably because people were tied up with spectre/meltdown stuff last time around. Still, the main pieces are: - Rework of our CPU features framework so that we can whitelist CPUs that don't require kpti even in a heterogeneous system - Support for the IDC/DIC architecture extensions, which allow us to elide instruction and data cache maintenance when writing out instructions - Removal of the large memory model which resulted in suboptimal codegen by the compiler and increased the use of literal pools, which could potentially be used as ROP gadgets since they are mapped as executable - Rework of forced signal delivery so that the siginfo_t is well-formed and handling of show_unhandled_signals is consolidated and made consistent between different fault types - More siginfo cleanup based on the initial patches from Eric Biederman - Workaround for Cortex-A55 erratum #1024718 - Some small ACPI IORT updates and cleanups from Lorenzo Pieralisi - Misc cleanups and non-critical fixes -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQEcBAABCgAGBQJaw1TCAAoJELescNyEwWM0gyQIAJVMK4QveBW+LwF96NYdZo16 p90Aa+nqKelh/s93govQArDMv1gxyuXdFlQZVOGPQHfqpz6RhJWmBA2tFsUbQrUc OBcioPrRihqTmKBe+1r1XORwZxkVX6GGmCn0LYpPR7I3TjxXZpvxqaxGxiUvHkci yVxWlDTyN/7eL3akhCpCDagN3Fxwk3QnJLqE3fxOFMlY7NvQcmUxcITiUl/s469q xK6SWH9SRH1JK8jTHPitwUBiU//3FfCqSI9HLEdDIDoTuPcVM8UetWvi4QzrzJL1 UYg8lmU0CXNmflDzZJDaMf+qFApOrGxR0YVPpBzlQvxe0JIY69g48f+JzDPz8nc= =+gNa -----END PGP SIGNATURE----- Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux Pull arm64 updates from Will Deacon: "Nothing particularly stands out here, probably because people were tied up with spectre/meltdown stuff last time around. Still, the main pieces are: - Rework of our CPU features framework so that we can whitelist CPUs that don't require kpti even in a heterogeneous system - Support for the IDC/DIC architecture extensions, which allow us to elide instruction and data cache maintenance when writing out instructions - Removal of the large memory model which resulted in suboptimal codegen by the compiler and increased the use of literal pools, which could potentially be used as ROP gadgets since they are mapped as executable - Rework of forced signal delivery so that the siginfo_t is well-formed and handling of show_unhandled_signals is consolidated and made consistent between different fault types - More siginfo cleanup based on the initial patches from Eric Biederman - Workaround for Cortex-A55 erratum #1024718 - Some small ACPI IORT updates and cleanups from Lorenzo Pieralisi - Misc cleanups and non-critical fixes" * tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: (70 commits) arm64: uaccess: Fix omissions from usercopy whitelist arm64: fpsimd: Split cpu field out from struct fpsimd_state arm64: tlbflush: avoid writing RES0 bits arm64: cmpxchg: Include linux/compiler.h in asm/cmpxchg.h arm64: move percpu cmpxchg implementation from cmpxchg.h to percpu.h arm64: cmpxchg: Include build_bug.h instead of bug.h for BUILD_BUG arm64: lse: Include compiler_types.h and export.h for out-of-line LL/SC arm64: fpsimd: include <linux/init.h> in fpsimd.h drivers/perf: arm_pmu_platform: do not warn about affinity on uniprocessor perf: arm_spe: include linux/vmalloc.h for vmap() Revert "arm64: Revert L1_CACHE_SHIFT back to 6 (64-byte cache line size)" arm64: cpufeature: Avoid warnings due to unused symbols arm64: Add work around for Arm Cortex-A55 Erratum 1024718 arm64: Delay enabling hardware DBM feature arm64: Add MIDR encoding for Arm Cortex-A55 and Cortex-A35 arm64: capabilities: Handle shared entries arm64: capabilities: Add support for checks based on a list of MIDRs arm64: Add helpers for checking CPU MIDR against a range arm64: capabilities: Clean up midr range helpers arm64: capabilities: Change scope of VHE to Boot CPU feature ...		2018-04-04 16:01:43 -07:00
..
cache.S	arm64: Add support for new control bits CTR_EL0.DIC and CTR_EL0.IDC	2018-03-09 13:57:57 +00:00
context.c	arm64: Move BP hardening to check_and_switch_context	2018-01-23 15:40:29 +00:00
copypage.c	arm64: Defer dcache flush in __cpu_copy_user_page	2015-12-17 11:07:13 +00:00
dma-mapping.c	Revert "arm64: Revert L1_CACHE_SHIFT back to 6 (64-byte cache line size)"	2018-03-27 12:04:51 +01:00
dump.c	arm64: mm: Use READ_ONCE/WRITE_ONCE when accessing page tables	2018-02-16 18:13:57 +00:00
extable.c	License cleanup: add SPDX GPL-2.0 license identifier to files with no license	2017-11-02 11:10:55 +01:00
fault.c	arm64: capabilities: Update prototype for enable call back	2018-03-26 18:00:37 +01:00
flush.c	arm64: fix pmem interface definition	2017-08-10 18:13:59 +01:00
hugetlbpage.c	arm64: mm: Use READ_ONCE/WRITE_ONCE when accessing page tables	2018-02-16 18:13:57 +00:00
init.c	Revert "arm64: Revert L1_CACHE_SHIFT back to 6 (64-byte cache line size)"	2018-03-27 12:04:51 +01:00
ioremap.c	arm64: use is_vmalloc_addr	2017-02-09 13:47:56 +00:00
kasan_init.c	arm64: mm: Use READ_ONCE/WRITE_ONCE when accessing page tables	2018-02-16 18:13:57 +00:00
Makefile	License cleanup: add SPDX GPL-2.0 license identifier to files with no license	2017-11-02 11:10:55 +01:00
mmap.c	arm64/mmap: properly account for stack randomization in mmap_base	2017-07-12 16:26:03 -07:00
mmu.c	mm/vmalloc: add interfaces to free unmapped page table	2018-03-22 17:07:01 -07:00
numa.c	arm64/numa: Drop duplicate message	2017-07-20 17:03:53 +01:00
pageattr.c	arm64: mm: Use READ_ONCE/WRITE_ONCE when accessing page tables	2018-02-16 18:13:57 +00:00
pgd.c	arm64: handle 52-bit addresses in TTBR	2017-12-22 17:35:21 +00:00
physaddr.c	License cleanup: add SPDX GPL-2.0 license identifier to files with no license	2017-11-02 11:10:55 +01:00
proc.S	arm64: Delay enabling hardware DBM feature	2018-03-26 18:01:44 +01:00
ptdump_debugfs.c	License cleanup: add SPDX GPL-2.0 license identifier to files with no license	2017-11-02 11:10:55 +01:00