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b7e8c9397c
Use unified assembler syntax (UAL) in inline assembler. Divided syntax is considered deprecated. This will also allow to build the kernel using LLVM's integrated assembler. When compiling non-Thumb2 GCC always emits a ".syntax divided" at the beginning of the inline assembly which makes the assembler fail. Since GCC 5 there is the -masm-syntax-unified GCC option which make GCC assume unified syntax asm and hence emits ".syntax unified" even in ARM mode. However, the option is broken since GCC version 6 (see GCC PR88648 [1]). Work around by adding ".syntax unified" as part of the inline assembly. [0] https://gcc.gnu.org/onlinedocs/gcc/ARM-Options.html#index-masm-syntax-unified [1] https://gcc.gnu.org/bugzilla/show_bug.cgi?id=88648 Signed-off-by: Stefan Agner <stefan@agner.ch> Acked-by: Nicolas Pitre <nico@linaro.org> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
96 lines
2.8 KiB
C
96 lines
2.8 KiB
C
/*
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* linux/arch/arm/mm/copypage-v4wb.c
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*
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* Copyright (C) 1995-1999 Russell King
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/highmem.h>
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/*
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* ARMv4 optimised copy_user_highpage
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*
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* We flush the destination cache lines just before we write the data into the
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* corresponding address. Since the Dcache is read-allocate, this removes the
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* Dcache aliasing issue. The writes will be forwarded to the write buffer,
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* and merged as appropriate.
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*
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* Note: We rely on all ARMv4 processors implementing the "invalidate D line"
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* instruction. If your processor does not supply this, you have to write your
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* own copy_user_highpage that does the right thing.
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*/
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static void v4wb_copy_user_page(void *kto, const void *kfrom)
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{
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int tmp;
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asm volatile ("\
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.syntax unified\n\
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ldmia %1!, {r3, r4, ip, lr} @ 4\n\
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1: mcr p15, 0, %0, c7, c6, 1 @ 1 invalidate D line\n\
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stmia %0!, {r3, r4, ip, lr} @ 4\n\
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ldmia %1!, {r3, r4, ip, lr} @ 4+1\n\
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stmia %0!, {r3, r4, ip, lr} @ 4\n\
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ldmia %1!, {r3, r4, ip, lr} @ 4\n\
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mcr p15, 0, %0, c7, c6, 1 @ 1 invalidate D line\n\
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stmia %0!, {r3, r4, ip, lr} @ 4\n\
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ldmia %1!, {r3, r4, ip, lr} @ 4\n\
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subs %2, %2, #1 @ 1\n\
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stmia %0!, {r3, r4, ip, lr} @ 4\n\
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ldmiane %1!, {r3, r4, ip, lr} @ 4\n\
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bne 1b @ 1\n\
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mcr p15, 0, %1, c7, c10, 4 @ 1 drain WB"
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: "+&r" (kto), "+&r" (kfrom), "=&r" (tmp)
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: "2" (PAGE_SIZE / 64)
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: "r3", "r4", "ip", "lr");
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}
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void v4wb_copy_user_highpage(struct page *to, struct page *from,
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unsigned long vaddr, struct vm_area_struct *vma)
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{
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void *kto, *kfrom;
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kto = kmap_atomic(to);
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kfrom = kmap_atomic(from);
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flush_cache_page(vma, vaddr, page_to_pfn(from));
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v4wb_copy_user_page(kto, kfrom);
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kunmap_atomic(kfrom);
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kunmap_atomic(kto);
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}
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/*
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* ARMv4 optimised clear_user_page
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*
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* Same story as above.
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*/
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void v4wb_clear_user_highpage(struct page *page, unsigned long vaddr)
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{
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void *ptr, *kaddr = kmap_atomic(page);
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asm volatile("\
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mov r1, %2 @ 1\n\
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mov r2, #0 @ 1\n\
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mov r3, #0 @ 1\n\
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mov ip, #0 @ 1\n\
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mov lr, #0 @ 1\n\
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1: mcr p15, 0, %0, c7, c6, 1 @ 1 invalidate D line\n\
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stmia %0!, {r2, r3, ip, lr} @ 4\n\
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stmia %0!, {r2, r3, ip, lr} @ 4\n\
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mcr p15, 0, %0, c7, c6, 1 @ 1 invalidate D line\n\
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stmia %0!, {r2, r3, ip, lr} @ 4\n\
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stmia %0!, {r2, r3, ip, lr} @ 4\n\
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subs r1, r1, #1 @ 1\n\
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bne 1b @ 1\n\
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mcr p15, 0, r1, c7, c10, 4 @ 1 drain WB"
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: "=r" (ptr)
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: "0" (kaddr), "I" (PAGE_SIZE / 64)
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: "r1", "r2", "r3", "ip", "lr");
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kunmap_atomic(kaddr);
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}
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struct cpu_user_fns v4wb_user_fns __initdata = {
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.cpu_clear_user_highpage = v4wb_clear_user_highpage,
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.cpu_copy_user_highpage = v4wb_copy_user_highpage,
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};
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