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0fdebc5ec2
Based on the normalized pattern:
this file is licensed under the terms of the gnu general public
license version 2 this program is licensed as is without any warranty
of any kind whether express or implied
extracted by the scancode license scanner the SPDX license identifier
GPL-2.0-only
has been chosen to replace the boilerplate/reference.
Reviewed-by: Allison Randal <allison@lohutok.net>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
70 lines
1.8 KiB
C
70 lines
1.8 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* arch/arm/mach-mv78xx0/irq.c
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*
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* MV78xx0 IRQ handling.
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*/
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#include <linux/gpio.h>
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#include <linux/kernel.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <asm/exception.h>
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#include <plat/orion-gpio.h>
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#include <plat/irq.h>
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#include "bridge-regs.h"
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#include "common.h"
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static int __initdata gpio0_irqs[4] = {
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IRQ_MV78XX0_GPIO_0_7,
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IRQ_MV78XX0_GPIO_8_15,
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IRQ_MV78XX0_GPIO_16_23,
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IRQ_MV78XX0_GPIO_24_31,
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};
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static void __iomem *mv78xx0_irq_base = IRQ_VIRT_BASE;
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static asmlinkage void
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__exception_irq_entry mv78xx0_legacy_handle_irq(struct pt_regs *regs)
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{
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u32 stat;
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stat = readl_relaxed(mv78xx0_irq_base + IRQ_CAUSE_LOW_OFF);
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stat &= readl_relaxed(mv78xx0_irq_base + IRQ_MASK_LOW_OFF);
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if (stat) {
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unsigned int hwirq = __fls(stat);
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handle_IRQ(hwirq, regs);
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return;
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}
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stat = readl_relaxed(mv78xx0_irq_base + IRQ_CAUSE_HIGH_OFF);
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stat &= readl_relaxed(mv78xx0_irq_base + IRQ_MASK_HIGH_OFF);
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if (stat) {
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unsigned int hwirq = 32 + __fls(stat);
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handle_IRQ(hwirq, regs);
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return;
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}
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stat = readl_relaxed(mv78xx0_irq_base + IRQ_CAUSE_ERR_OFF);
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stat &= readl_relaxed(mv78xx0_irq_base + IRQ_MASK_ERR_OFF);
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if (stat) {
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unsigned int hwirq = 64 + __fls(stat);
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handle_IRQ(hwirq, regs);
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return;
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}
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}
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void __init mv78xx0_init_irq(void)
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{
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orion_irq_init(0, IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF);
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orion_irq_init(32, IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF);
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orion_irq_init(64, IRQ_VIRT_BASE + IRQ_MASK_ERR_OFF);
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set_handle_irq(mv78xx0_legacy_handle_irq);
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/*
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* Initialize gpiolib for GPIOs 0-31. (The GPIO interrupt mask
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* registers for core #1 are at an offset of 0x18 from those of
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* core #0.)
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*/
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orion_gpio_init(0, 32, GPIO_VIRT_BASE, mv78xx0_core_index() ? 0x18 : 0,
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IRQ_MV78XX0_GPIO_START, gpio0_irqs);
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}
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