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529322112a
Use V4L2 CCI for accessing device's registers. The 8-bit compatibility read option is removed but this is supported by regmap through other means. Also the CCS register definitions are re-generated with V4L2 CCI definitions. The older SMIA++ register definitions have been manually converted. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
959 lines
51 KiB
C
959 lines
51 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause */
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/* Copyright (C) 2019--2020 Intel Corporation */
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/*
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* Generated by Documentation/driver-api/media/drivers/ccs/mk-ccs-regs;
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* do not modify.
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*/
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#ifndef __CCS_REGS_H__
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#define __CCS_REGS_H__
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#include <linux/bits.h>
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#include <media/v4l2-cci.h>
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#define CCS_FL_BASE CCI_REG_PRIVATE_SHIFT
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#define CCS_FL_FLOAT_IREAL BIT(CCS_FL_BASE)
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#define CCS_FL_IREAL BIT(CCS_FL_BASE + 1)
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#define CCS_BUILD_BUG \
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BUILD_BUG_ON(~CCI_REG_PRIVATE_MASK & (BIT(CCS_FL_BASE) | BIT(CCS_FL_BASE + 1)))
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#define CCS_R_MODULE_MODEL_ID CCI_REG16(0x0000)
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#define CCS_R_MODULE_REVISION_NUMBER_MAJOR CCI_REG8(0x0002)
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#define CCS_R_FRAME_COUNT CCI_REG8(0x0005)
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#define CCS_R_PIXEL_ORDER CCI_REG8(0x0006)
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#define CCS_PIXEL_ORDER_GRBG 0U
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#define CCS_PIXEL_ORDER_RGGB 1U
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#define CCS_PIXEL_ORDER_BGGR 2U
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#define CCS_PIXEL_ORDER_GBRG 3U
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#define CCS_R_MIPI_CCS_VERSION CCI_REG8(0x0007)
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#define CCS_MIPI_CCS_VERSION_V1_0 0x10
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#define CCS_MIPI_CCS_VERSION_V1_1 0x11
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#define CCS_MIPI_CCS_VERSION_MAJOR_SHIFT 4U
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#define CCS_MIPI_CCS_VERSION_MAJOR_MASK 0xf0
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#define CCS_MIPI_CCS_VERSION_MINOR_SHIFT 0U
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#define CCS_MIPI_CCS_VERSION_MINOR_MASK 0xf
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#define CCS_R_DATA_PEDESTAL CCI_REG16(0x0008)
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#define CCS_R_MODULE_MANUFACTURER_ID CCI_REG16(0x000e)
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#define CCS_R_MODULE_REVISION_NUMBER_MINOR CCI_REG8(0x0010)
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#define CCS_R_MODULE_DATE_YEAR CCI_REG8(0x0012)
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#define CCS_R_MODULE_DATE_MONTH CCI_REG8(0x0013)
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#define CCS_R_MODULE_DATE_DAY CCI_REG8(0x0014)
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#define CCS_R_MODULE_DATE_PHASE CCI_REG8(0x0015)
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#define CCS_MODULE_DATE_PHASE_SHIFT 0U
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#define CCS_MODULE_DATE_PHASE_MASK 0x7
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#define CCS_MODULE_DATE_PHASE_TS 0U
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#define CCS_MODULE_DATE_PHASE_ES 1U
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#define CCS_MODULE_DATE_PHASE_CS 2U
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#define CCS_MODULE_DATE_PHASE_MP 3U
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#define CCS_R_SENSOR_MODEL_ID CCI_REG16(0x0016)
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#define CCS_R_SENSOR_REVISION_NUMBER CCI_REG8(0x0018)
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#define CCS_R_SENSOR_FIRMWARE_VERSION CCI_REG8(0x001a)
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#define CCS_R_SERIAL_NUMBER CCI_REG32(0x001c)
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#define CCS_R_SENSOR_MANUFACTURER_ID CCI_REG16(0x0020)
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#define CCS_R_SENSOR_REVISION_NUMBER_16 CCI_REG16(0x0022)
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#define CCS_R_FRAME_FORMAT_MODEL_TYPE CCI_REG8(0x0040)
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#define CCS_FRAME_FORMAT_MODEL_TYPE_2_BYTE 1U
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#define CCS_FRAME_FORMAT_MODEL_TYPE_4_BYTE 2U
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#define CCS_R_FRAME_FORMAT_MODEL_SUBTYPE CCI_REG8(0x0041)
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#define CCS_FRAME_FORMAT_MODEL_SUBTYPE_ROWS_SHIFT 0U
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#define CCS_FRAME_FORMAT_MODEL_SUBTYPE_ROWS_MASK 0xf
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#define CCS_FRAME_FORMAT_MODEL_SUBTYPE_COLUMNS_SHIFT 4U
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#define CCS_FRAME_FORMAT_MODEL_SUBTYPE_COLUMNS_MASK 0xf0
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#define CCS_R_FRAME_FORMAT_DESCRIPTOR(n) CCI_REG16(0x0042 + (n) * 2)
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#define CCS_LIM_FRAME_FORMAT_DESCRIPTOR_MIN_N 0U
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#define CCS_LIM_FRAME_FORMAT_DESCRIPTOR_MAX_N 14U
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#define CCS_R_FRAME_FORMAT_DESCRIPTOR_4(n) CCI_REG32(0x0060 + (n) * 4)
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#define CCS_FRAME_FORMAT_DESCRIPTOR_PIXELS_SHIFT 0U
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#define CCS_FRAME_FORMAT_DESCRIPTOR_PIXELS_MASK 0xfff
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#define CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_SHIFT 12U
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#define CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_MASK 0xf000
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#define CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_EMBEDDED 1U
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#define CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_DUMMY_PIXEL 2U
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#define CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_BLACK_PIXEL 3U
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#define CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_DARK_PIXEL 4U
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#define CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_VISIBLE_PIXEL 5U
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#define CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_MANUF_SPECIFIC_0 8U
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#define CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_MANUF_SPECIFIC_1 9U
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#define CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_MANUF_SPECIFIC_2 10U
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#define CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_MANUF_SPECIFIC_3 11U
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#define CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_MANUF_SPECIFIC_4 12U
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#define CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_MANUF_SPECIFIC_5 13U
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#define CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_MANUF_SPECIFIC_6 14U
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#define CCS_LIM_FRAME_FORMAT_DESCRIPTOR_4_MIN_N 0U
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#define CCS_LIM_FRAME_FORMAT_DESCRIPTOR_4_MAX_N 7U
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#define CCS_FRAME_FORMAT_DESCRIPTOR_4_PIXELS_SHIFT 0U
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#define CCS_FRAME_FORMAT_DESCRIPTOR_4_PIXELS_MASK 0xffff
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#define CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_SHIFT 28U
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#define CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_MASK 0xf0000000
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#define CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_EMBEDDED 1U
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#define CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_DUMMY_PIXEL 2U
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#define CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_BLACK_PIXEL 3U
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#define CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_DARK_PIXEL 4U
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#define CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_VISIBLE_PIXEL 5U
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#define CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_MANUF_SPECIFIC_0 8U
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#define CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_MANUF_SPECIFIC_1 9U
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#define CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_MANUF_SPECIFIC_2 10U
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#define CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_MANUF_SPECIFIC_3 11U
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#define CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_MANUF_SPECIFIC_4 12U
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#define CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_MANUF_SPECIFIC_5 13U
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#define CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_MANUF_SPECIFIC_6 14U
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#define CCS_R_ANALOG_GAIN_CAPABILITY CCI_REG16(0x0080)
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#define CCS_ANALOG_GAIN_CAPABILITY_GLOBAL 0U
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#define CCS_ANALOG_GAIN_CAPABILITY_ALTERNATE_GLOBAL 2U
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#define CCS_R_ANALOG_GAIN_CODE_MIN CCI_REG16(0x0084)
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#define CCS_R_ANALOG_GAIN_CODE_MAX CCI_REG16(0x0086)
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#define CCS_R_ANALOG_GAIN_CODE_STEP CCI_REG16(0x0088)
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#define CCS_R_ANALOG_GAIN_TYPE CCI_REG16(0x008a)
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#define CCS_R_ANALOG_GAIN_M0 CCI_REG16(0x008c)
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#define CCS_R_ANALOG_GAIN_C0 CCI_REG16(0x008e)
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#define CCS_R_ANALOG_GAIN_M1 CCI_REG16(0x0090)
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#define CCS_R_ANALOG_GAIN_C1 CCI_REG16(0x0092)
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#define CCS_R_ANALOG_LINEAR_GAIN_MIN CCI_REG16(0x0094)
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#define CCS_R_ANALOG_LINEAR_GAIN_MAX CCI_REG16(0x0096)
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#define CCS_R_ANALOG_LINEAR_GAIN_STEP_SIZE CCI_REG16(0x0098)
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#define CCS_R_ANALOG_EXPONENTIAL_GAIN_MIN CCI_REG16(0x009a)
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#define CCS_R_ANALOG_EXPONENTIAL_GAIN_MAX CCI_REG16(0x009c)
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#define CCS_R_ANALOG_EXPONENTIAL_GAIN_STEP_SIZE CCI_REG16(0x009e)
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#define CCS_R_DATA_FORMAT_MODEL_TYPE CCI_REG8(0x00c0)
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#define CCS_DATA_FORMAT_MODEL_TYPE_NORMAL 1U
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#define CCS_DATA_FORMAT_MODEL_TYPE_EXTENDED 2U
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#define CCS_R_DATA_FORMAT_MODEL_SUBTYPE CCI_REG8(0x00c1)
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#define CCS_DATA_FORMAT_MODEL_SUBTYPE_ROWS_SHIFT 0U
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#define CCS_DATA_FORMAT_MODEL_SUBTYPE_ROWS_MASK 0xf
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#define CCS_DATA_FORMAT_MODEL_SUBTYPE_COLUMNS_SHIFT 4U
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#define CCS_DATA_FORMAT_MODEL_SUBTYPE_COLUMNS_MASK 0xf0
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#define CCS_R_DATA_FORMAT_DESCRIPTOR(n) CCI_REG16(0x00c2 + (n) * 2)
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#define CCS_LIM_DATA_FORMAT_DESCRIPTOR_MIN_N 0U
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#define CCS_LIM_DATA_FORMAT_DESCRIPTOR_MAX_N 15U
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#define CCS_DATA_FORMAT_DESCRIPTOR_COMPRESSED_SHIFT 0U
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#define CCS_DATA_FORMAT_DESCRIPTOR_COMPRESSED_MASK 0xff
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#define CCS_DATA_FORMAT_DESCRIPTOR_UNCOMPRESSED_SHIFT 8U
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#define CCS_DATA_FORMAT_DESCRIPTOR_UNCOMPRESSED_MASK 0xff00
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#define CCS_R_MODE_SELECT CCI_REG8(0x0100)
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#define CCS_MODE_SELECT_SOFTWARE_STANDBY 0U
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#define CCS_MODE_SELECT_STREAMING 1U
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#define CCS_R_IMAGE_ORIENTATION CCI_REG8(0x0101)
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#define CCS_IMAGE_ORIENTATION_HORIZONTAL_MIRROR BIT(0)
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#define CCS_IMAGE_ORIENTATION_VERTICAL_FLIP BIT(1)
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#define CCS_R_SOFTWARE_RESET CCI_REG8(0x0103)
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#define CCS_SOFTWARE_RESET_OFF 0U
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#define CCS_SOFTWARE_RESET_ON 1U
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#define CCS_R_GROUPED_PARAMETER_HOLD CCI_REG8(0x0104)
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#define CCS_R_MASK_CORRUPTED_FRAMES CCI_REG8(0x0105)
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#define CCS_MASK_CORRUPTED_FRAMES_ALLOW 0U
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#define CCS_MASK_CORRUPTED_FRAMES_MASK 1U
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#define CCS_R_FAST_STANDBY_CTRL CCI_REG8(0x0106)
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#define CCS_FAST_STANDBY_CTRL_COMPLETE_FRAMES 0U
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#define CCS_FAST_STANDBY_CTRL_FRAME_TRUNCATION 1U
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#define CCS_R_CCI_ADDRESS_CTRL CCI_REG8(0x0107)
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#define CCS_R_2ND_CCI_IF_CTRL CCI_REG8(0x0108)
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#define CCS_2ND_CCI_IF_CTRL_ENABLE BIT(0)
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#define CCS_2ND_CCI_IF_CTRL_ACK BIT(1)
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#define CCS_R_2ND_CCI_ADDRESS_CTRL CCI_REG8(0x0109)
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#define CCS_R_CSI_CHANNEL_IDENTIFIER CCI_REG8(0x0110)
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#define CCS_R_CSI_SIGNALING_MODE CCI_REG8(0x0111)
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#define CCS_CSI_SIGNALING_MODE_CSI_2_DPHY 2U
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#define CCS_CSI_SIGNALING_MODE_CSI_2_CPHY 3U
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#define CCS_R_CSI_DATA_FORMAT CCI_REG16(0x0112)
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#define CCS_R_CSI_LANE_MODE CCI_REG8(0x0114)
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#define CCS_R_DPCM_FRAME_DT CCI_REG8(0x011d)
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#define CCS_R_BOTTOM_EMBEDDED_DATA_DT CCI_REG8(0x011e)
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#define CCS_R_BOTTOM_EMBEDDED_DATA_VC CCI_REG8(0x011f)
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#define CCS_R_GAIN_MODE CCI_REG8(0x0120)
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#define CCS_GAIN_MODE_GLOBAL 0U
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#define CCS_GAIN_MODE_ALTERNATE 1U
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#define CCS_R_ADC_BIT_DEPTH CCI_REG8(0x0121)
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#define CCS_R_EMB_DATA_CTRL CCI_REG8(0x0122)
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#define CCS_EMB_DATA_CTRL_RAW8_PACKING_FOR_RAW16 BIT(0)
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#define CCS_EMB_DATA_CTRL_RAW10_PACKING_FOR_RAW20 BIT(1)
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#define CCS_EMB_DATA_CTRL_RAW12_PACKING_FOR_RAW24 BIT(2)
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#define CCS_R_GPIO_TRIG_MODE CCI_REG8(0x0130)
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#define CCS_R_EXTCLK_FREQUENCY_MHZ (CCI_REG16(0x0136) | CCS_FL_IREAL)
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#define CCS_R_TEMP_SENSOR_CTRL CCI_REG8(0x0138)
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#define CCS_TEMP_SENSOR_CTRL_ENABLE BIT(0)
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#define CCS_R_TEMP_SENSOR_MODE CCI_REG8(0x0139)
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#define CCS_R_TEMP_SENSOR_OUTPUT CCI_REG8(0x013a)
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#define CCS_R_FINE_INTEGRATION_TIME CCI_REG16(0x0200)
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#define CCS_R_COARSE_INTEGRATION_TIME CCI_REG16(0x0202)
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#define CCS_R_ANALOG_GAIN_CODE_GLOBAL CCI_REG16(0x0204)
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#define CCS_R_ANALOG_LINEAR_GAIN_GLOBAL CCI_REG16(0x0206)
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#define CCS_R_ANALOG_EXPONENTIAL_GAIN_GLOBAL CCI_REG16(0x0208)
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#define CCS_R_DIGITAL_GAIN_GLOBAL CCI_REG16(0x020e)
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#define CCS_R_SHORT_ANALOG_GAIN_GLOBAL CCI_REG16(0x0216)
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#define CCS_R_SHORT_DIGITAL_GAIN_GLOBAL CCI_REG16(0x0218)
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#define CCS_R_HDR_MODE CCI_REG8(0x0220)
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#define CCS_HDR_MODE_ENABLED BIT(0)
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#define CCS_HDR_MODE_SEPARATE_ANALOG_GAIN BIT(1)
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#define CCS_HDR_MODE_UPSCALING BIT(2)
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#define CCS_HDR_MODE_RESET_SYNC BIT(3)
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#define CCS_HDR_MODE_TIMING_MODE BIT(4)
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#define CCS_HDR_MODE_EXPOSURE_CTRL_DIRECT BIT(5)
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#define CCS_HDR_MODE_SEPARATE_DIGITAL_GAIN BIT(6)
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#define CCS_R_HDR_RESOLUTION_REDUCTION CCI_REG8(0x0221)
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#define CCS_HDR_RESOLUTION_REDUCTION_ROW_SHIFT 0U
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#define CCS_HDR_RESOLUTION_REDUCTION_ROW_MASK 0xf
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#define CCS_HDR_RESOLUTION_REDUCTION_COLUMN_SHIFT 4U
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#define CCS_HDR_RESOLUTION_REDUCTION_COLUMN_MASK 0xf0
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#define CCS_R_EXPOSURE_RATIO CCI_REG8(0x0222)
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#define CCS_R_HDR_INTERNAL_BIT_DEPTH CCI_REG8(0x0223)
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#define CCS_R_DIRECT_SHORT_INTEGRATION_TIME CCI_REG16(0x0224)
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#define CCS_R_SHORT_ANALOG_LINEAR_GAIN_GLOBAL CCI_REG16(0x0226)
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#define CCS_R_SHORT_ANALOG_EXPONENTIAL_GAIN_GLOBAL CCI_REG16(0x0228)
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#define CCS_R_VT_PIX_CLK_DIV CCI_REG16(0x0300)
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#define CCS_R_VT_SYS_CLK_DIV CCI_REG16(0x0302)
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#define CCS_R_PRE_PLL_CLK_DIV CCI_REG16(0x0304)
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#define CCS_R_PLL_MULTIPLIER CCI_REG16(0x0306)
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#define CCS_R_OP_PIX_CLK_DIV CCI_REG16(0x0308)
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#define CCS_R_OP_SYS_CLK_DIV CCI_REG16(0x030a)
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#define CCS_R_OP_PRE_PLL_CLK_DIV CCI_REG16(0x030c)
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#define CCS_R_OP_PLL_MULTIPLIER CCI_REG16(0x030e)
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#define CCS_R_PLL_MODE CCI_REG8(0x0310)
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#define CCS_PLL_MODE_SHIFT 0U
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#define CCS_PLL_MODE_MASK 0x1
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#define CCS_PLL_MODE_SINGLE 0U
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#define CCS_PLL_MODE_DUAL 1U
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#define CCS_R_OP_PIX_CLK_DIV_REV CCI_REG16(0x0312)
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#define CCS_R_OP_SYS_CLK_DIV_REV CCI_REG16(0x0314)
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#define CCS_R_FRAME_LENGTH_LINES CCI_REG16(0x0340)
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#define CCS_R_LINE_LENGTH_PCK CCI_REG16(0x0342)
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#define CCS_R_X_ADDR_START CCI_REG16(0x0344)
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#define CCS_R_Y_ADDR_START CCI_REG16(0x0346)
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#define CCS_R_X_ADDR_END CCI_REG16(0x0348)
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#define CCS_R_Y_ADDR_END CCI_REG16(0x034a)
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#define CCS_R_X_OUTPUT_SIZE CCI_REG16(0x034c)
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#define CCS_R_Y_OUTPUT_SIZE CCI_REG16(0x034e)
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#define CCS_R_FRAME_LENGTH_CTRL CCI_REG8(0x0350)
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#define CCS_FRAME_LENGTH_CTRL_AUTOMATIC BIT(0)
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#define CCS_R_TIMING_MODE_CTRL CCI_REG8(0x0352)
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#define CCS_TIMING_MODE_CTRL_MANUAL_READOUT BIT(0)
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#define CCS_TIMING_MODE_CTRL_DELAYED_EXPOSURE BIT(1)
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#define CCS_R_START_READOUT_RS CCI_REG8(0x0353)
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#define CCS_START_READOUT_RS_MANUAL_READOUT_START BIT(0)
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#define CCS_R_FRAME_MARGIN CCI_REG16(0x0354)
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#define CCS_R_X_EVEN_INC CCI_REG16(0x0380)
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#define CCS_R_X_ODD_INC CCI_REG16(0x0382)
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#define CCS_R_Y_EVEN_INC CCI_REG16(0x0384)
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#define CCS_R_Y_ODD_INC CCI_REG16(0x0386)
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#define CCS_R_MONOCHROME_EN CCI_REG8(0x0390)
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#define CCS_MONOCHROME_EN_ENABLED 0U
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#define CCS_R_SCALING_MODE CCI_REG16(0x0400)
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#define CCS_SCALING_MODE_NO_SCALING 0U
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#define CCS_SCALING_MODE_HORIZONTAL 1U
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#define CCS_R_SCALE_M CCI_REG16(0x0404)
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#define CCS_R_SCALE_N CCI_REG16(0x0406)
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#define CCS_R_DIGITAL_CROP_X_OFFSET CCI_REG16(0x0408)
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#define CCS_R_DIGITAL_CROP_Y_OFFSET CCI_REG16(0x040a)
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#define CCS_R_DIGITAL_CROP_IMAGE_WIDTH CCI_REG16(0x040c)
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#define CCS_R_DIGITAL_CROP_IMAGE_HEIGHT CCI_REG16(0x040e)
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#define CCS_R_COMPRESSION_MODE CCI_REG16(0x0500)
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#define CCS_COMPRESSION_MODE_NONE 0U
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#define CCS_COMPRESSION_MODE_DPCM_PCM_SIMPLE 1U
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#define CCS_R_TEST_PATTERN_MODE CCI_REG16(0x0600)
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#define CCS_TEST_PATTERN_MODE_NONE 0U
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#define CCS_TEST_PATTERN_MODE_SOLID_COLOR 1U
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#define CCS_TEST_PATTERN_MODE_COLOR_BARS 2U
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#define CCS_TEST_PATTERN_MODE_FADE_TO_GREY 3U
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#define CCS_TEST_PATTERN_MODE_PN9 4U
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#define CCS_TEST_PATTERN_MODE_COLOR_TILE 5U
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#define CCS_R_TEST_DATA_RED CCI_REG16(0x0602)
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#define CCS_R_TEST_DATA_GREENR CCI_REG16(0x0604)
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#define CCS_R_TEST_DATA_BLUE CCI_REG16(0x0606)
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#define CCS_R_TEST_DATA_GREENB CCI_REG16(0x0608)
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#define CCS_R_VALUE_STEP_SIZE_SMOOTH CCI_REG8(0x060a)
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#define CCS_R_VALUE_STEP_SIZE_QUANTISED CCI_REG8(0x060b)
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#define CCS_R_TCLK_POST CCI_REG8(0x0800)
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#define CCS_R_THS_PREPARE CCI_REG8(0x0801)
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#define CCS_R_THS_ZERO_MIN CCI_REG8(0x0802)
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#define CCS_R_THS_TRAIL CCI_REG8(0x0803)
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#define CCS_R_TCLK_TRAIL_MIN CCI_REG8(0x0804)
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#define CCS_R_TCLK_PREPARE CCI_REG8(0x0805)
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#define CCS_R_TCLK_ZERO CCI_REG8(0x0806)
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#define CCS_R_TLPX CCI_REG8(0x0807)
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#define CCS_R_PHY_CTRL CCI_REG8(0x0808)
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#define CCS_PHY_CTRL_AUTO 0U
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#define CCS_PHY_CTRL_UI 1U
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#define CCS_PHY_CTRL_MANUAL 2U
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#define CCS_R_TCLK_POST_EX CCI_REG16(0x080a)
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#define CCS_R_THS_PREPARE_EX CCI_REG16(0x080c)
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#define CCS_R_THS_ZERO_MIN_EX CCI_REG16(0x080e)
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#define CCS_R_THS_TRAIL_EX CCI_REG16(0x0810)
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#define CCS_R_TCLK_TRAIL_MIN_EX CCI_REG16(0x0812)
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#define CCS_R_TCLK_PREPARE_EX CCI_REG16(0x0814)
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#define CCS_R_TCLK_ZERO_EX CCI_REG16(0x0816)
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#define CCS_R_TLPX_EX CCI_REG16(0x0818)
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#define CCS_R_REQUESTED_LINK_RATE CCI_REG32(0x0820)
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#define CCS_R_DPHY_EQUALIZATION_MODE CCI_REG8(0x0824)
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#define CCS_DPHY_EQUALIZATION_MODE_EQ2 BIT(0)
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#define CCS_R_PHY_EQUALIZATION_CTRL CCI_REG8(0x0825)
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#define CCS_PHY_EQUALIZATION_CTRL_ENABLE BIT(0)
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#define CCS_R_DPHY_PREAMBLE_CTRL CCI_REG8(0x0826)
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#define CCS_DPHY_PREAMBLE_CTRL_ENABLE BIT(0)
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#define CCS_R_DPHY_PREAMBLE_LENGTH CCI_REG8(0x0826)
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#define CCS_R_PHY_SSC_CTRL CCI_REG8(0x0828)
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#define CCS_PHY_SSC_CTRL_ENABLE BIT(0)
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#define CCS_R_MANUAL_LP_CTRL CCI_REG8(0x0829)
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#define CCS_MANUAL_LP_CTRL_ENABLE BIT(0)
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#define CCS_R_TWAKEUP CCI_REG8(0x082a)
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#define CCS_R_TINIT CCI_REG8(0x082b)
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#define CCS_R_THS_EXIT CCI_REG8(0x082c)
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#define CCS_R_THS_EXIT_EX CCI_REG16(0x082e)
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#define CCS_R_PHY_PERIODIC_CALIBRATION_CTRL CCI_REG8(0x0830)
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#define CCS_PHY_PERIODIC_CALIBRATION_CTRL_FRAME_BLANKING BIT(0)
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#define CCS_R_PHY_PERIODIC_CALIBRATION_INTERVAL CCI_REG8(0x0831)
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#define CCS_R_PHY_INIT_CALIBRATION_CTRL CCI_REG8(0x0832)
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#define CCS_PHY_INIT_CALIBRATION_CTRL_STREAM_START BIT(0)
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#define CCS_R_DPHY_CALIBRATION_MODE CCI_REG8(0x0833)
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#define CCS_DPHY_CALIBRATION_MODE_ALSO_ALTERNATE BIT(0)
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#define CCS_R_CPHY_CALIBRATION_MODE CCI_REG8(0x0834)
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#define CCS_CPHY_CALIBRATION_MODE_FORMAT_1 0U
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#define CCS_CPHY_CALIBRATION_MODE_FORMAT_2 1U
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#define CCS_CPHY_CALIBRATION_MODE_FORMAT_3 2U
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#define CCS_R_T3_CALPREAMBLE_LENGTH CCI_REG8(0x0835)
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#define CCS_R_T3_CALPREAMBLE_LENGTH_PER CCI_REG8(0x0836)
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#define CCS_R_T3_CALALTSEQ_LENGTH CCI_REG8(0x0837)
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#define CCS_R_T3_CALALTSEQ_LENGTH_PER CCI_REG8(0x0838)
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#define CCS_R_FM2_INIT_SEED CCI_REG16(0x083a)
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#define CCS_R_T3_CALUDEFSEQ_LENGTH CCI_REG16(0x083c)
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#define CCS_R_T3_CALUDEFSEQ_LENGTH_PER CCI_REG16(0x083e)
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#define CCS_R_TGR_PREAMBLE_LENGTH CCI_REG8(0x0841)
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#define CCS_TGR_PREAMBLE_LENGTH_PREAMABLE_PROG_SEQ BIT(7)
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#define CCS_TGR_PREAMBLE_LENGTH_BEGIN_PREAMBLE_LENGTH_SHIFT 0U
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#define CCS_TGR_PREAMBLE_LENGTH_BEGIN_PREAMBLE_LENGTH_MASK 0x3f
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#define CCS_R_TGR_POST_LENGTH CCI_REG8(0x0842)
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#define CCS_TGR_POST_LENGTH_POST_LENGTH_SHIFT 0U
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#define CCS_TGR_POST_LENGTH_POST_LENGTH_MASK 0x1f
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#define CCS_R_TGR_PREAMBLE_PROG_SEQUENCE(n2) CCI_REG8(0x0843 + (n2))
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#define CCS_LIM_TGR_PREAMBLE_PROG_SEQUENCE_MIN_N2 0U
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#define CCS_LIM_TGR_PREAMBLE_PROG_SEQUENCE_MAX_N2 6U
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#define CCS_TGR_PREAMBLE_PROG_SEQUENCE_SYMBOL_N_1_SHIFT 3U
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#define CCS_TGR_PREAMBLE_PROG_SEQUENCE_SYMBOL_N_1_MASK 0x38
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#define CCS_TGR_PREAMBLE_PROG_SEQUENCE_SYMBOL_N_SHIFT 0U
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#define CCS_TGR_PREAMBLE_PROG_SEQUENCE_SYMBOL_N_MASK 0x7
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#define CCS_R_T3_PREPARE CCI_REG16(0x084e)
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#define CCS_R_T3_LPX CCI_REG16(0x0850)
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#define CCS_R_ALPS_CTRL CCI_REG8(0x085a)
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#define CCS_ALPS_CTRL_LVLP_DPHY BIT(0)
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#define CCS_ALPS_CTRL_LVLP_CPHY BIT(1)
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#define CCS_ALPS_CTRL_ALP_CPHY BIT(2)
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#define CCS_R_TX_REG_CSI_EPD_EN_SSP_CPHY CCI_REG16(0x0860)
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#define CCS_R_TX_REG_CSI_EPD_OP_SLP_CPHY CCI_REG16(0x0862)
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#define CCS_R_TX_REG_CSI_EPD_EN_SSP_DPHY CCI_REG16(0x0864)
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#define CCS_R_TX_REG_CSI_EPD_OP_SLP_DPHY CCI_REG16(0x0866)
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#define CCS_R_TX_REG_CSI_EPD_MISC_OPTION_CPHY CCI_REG8(0x0868)
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#define CCS_R_TX_REG_CSI_EPD_MISC_OPTION_DPHY CCI_REG8(0x0869)
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#define CCS_R_SCRAMBLING_CTRL CCI_REG8(0x0870)
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#define CCS_SCRAMBLING_CTRL_ENABLED BIT(0)
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#define CCS_SCRAMBLING_CTRL_SHIFT 2U
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#define CCS_SCRAMBLING_CTRL_MASK 0xc
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#define CCS_SCRAMBLING_CTRL_1_SEED_CPHY 0U
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#define CCS_SCRAMBLING_CTRL_4_SEED_CPHY 3U
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#define CCS_R_LANE_SEED_VALUE(seed, lane) CCI_REG16(0x0872 + (seed) * 16 + (lane) * 2)
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#define CCS_LIM_LANE_SEED_VALUE_MIN_SEED 0U
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#define CCS_LIM_LANE_SEED_VALUE_MAX_SEED 3U
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#define CCS_LIM_LANE_SEED_VALUE_MIN_LANE 0U
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#define CCS_LIM_LANE_SEED_VALUE_MAX_LANE 7U
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#define CCS_R_TX_USL_REV_ENTRY CCI_REG16(0x08c0)
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#define CCS_R_TX_USL_REV_CLOCK_COUNTER CCI_REG16(0x08c2)
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#define CCS_R_TX_USL_REV_LP_COUNTER CCI_REG16(0x08c4)
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#define CCS_R_TX_USL_REV_FRAME_COUNTER CCI_REG16(0x08c6)
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#define CCS_R_TX_USL_REV_CHRONOLOGICAL_TIMER CCI_REG16(0x08c8)
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#define CCS_R_TX_USL_FWD_ENTRY CCI_REG16(0x08ca)
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#define CCS_R_TX_USL_GPIO CCI_REG16(0x08cc)
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#define CCS_R_TX_USL_OPERATION CCI_REG16(0x08ce)
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#define CCS_TX_USL_OPERATION_RESET BIT(0)
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#define CCS_R_TX_USL_ALP_CTRL CCI_REG16(0x08d0)
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#define CCS_TX_USL_ALP_CTRL_CLOCK_PAUSE BIT(0)
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#define CCS_R_TX_USL_APP_BTA_ACK_TIMEOUT CCI_REG16(0x08d2)
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#define CCS_R_TX_USL_SNS_BTA_ACK_TIMEOUT CCI_REG16(0x08d2)
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#define CCS_R_USL_CLOCK_MODE_D_CTRL CCI_REG8(0x08d2)
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#define CCS_USL_CLOCK_MODE_D_CTRL_CONT_CLOCK_STANDBY BIT(0)
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#define CCS_USL_CLOCK_MODE_D_CTRL_CONT_CLOCK_VBLANK BIT(1)
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#define CCS_USL_CLOCK_MODE_D_CTRL_CONT_CLOCK_HBLANK BIT(2)
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#define CCS_R_BINNING_MODE CCI_REG8(0x0900)
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#define CCS_R_BINNING_TYPE CCI_REG8(0x0901)
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#define CCS_R_BINNING_WEIGHTING CCI_REG8(0x0902)
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#define CCS_R_DATA_TRANSFER_IF_1_CTRL CCI_REG8(0x0a00)
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#define CCS_DATA_TRANSFER_IF_1_CTRL_ENABLE BIT(0)
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#define CCS_DATA_TRANSFER_IF_1_CTRL_WRITE BIT(1)
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#define CCS_DATA_TRANSFER_IF_1_CTRL_CLEAR_ERROR BIT(2)
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#define CCS_R_DATA_TRANSFER_IF_1_STATUS CCI_REG8(0x0a01)
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#define CCS_DATA_TRANSFER_IF_1_STATUS_READ_IF_READY BIT(0)
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#define CCS_DATA_TRANSFER_IF_1_STATUS_WRITE_IF_READY BIT(1)
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#define CCS_DATA_TRANSFER_IF_1_STATUS_DATA_CORRUPTED BIT(2)
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#define CCS_DATA_TRANSFER_IF_1_STATUS_IMPROPER_IF_USAGE BIT(3)
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#define CCS_R_DATA_TRANSFER_IF_1_PAGE_SELECT CCI_REG8(0x0a02)
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#define CCS_R_DATA_TRANSFER_IF_1_DATA(p) CCI_REG8(0x0a04 + (p))
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#define CCS_LIM_DATA_TRANSFER_IF_1_DATA_MIN_P 0U
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#define CCS_LIM_DATA_TRANSFER_IF_1_DATA_MAX_P 63U
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#define CCS_R_SHADING_CORRECTION_EN CCI_REG8(0x0b00)
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#define CCS_SHADING_CORRECTION_EN_ENABLE BIT(0)
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#define CCS_R_LUMINANCE_CORRECTION_LEVEL CCI_REG8(0x0b01)
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#define CCS_R_GREEN_IMBALANCE_FILTER_EN CCI_REG8(0x0b02)
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#define CCS_GREEN_IMBALANCE_FILTER_EN_ENABLE BIT(0)
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#define CCS_R_MAPPED_DEFECT_CORRECT_EN CCI_REG8(0x0b05)
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#define CCS_MAPPED_DEFECT_CORRECT_EN_ENABLE BIT(0)
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#define CCS_R_SINGLE_DEFECT_CORRECT_EN CCI_REG8(0x0b06)
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#define CCS_SINGLE_DEFECT_CORRECT_EN_ENABLE BIT(0)
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#define CCS_R_DYNAMIC_COUPLET_CORRECT_EN CCI_REG8(0x0b08)
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#define CCS_DYNAMIC_COUPLET_CORRECT_EN_ENABLE BIT(0)
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#define CCS_R_COMBINED_DEFECT_CORRECT_EN CCI_REG8(0x0b0a)
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#define CCS_COMBINED_DEFECT_CORRECT_EN_ENABLE BIT(0)
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#define CCS_R_MODULE_SPECIFIC_CORRECTION_EN CCI_REG8(0x0b0c)
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#define CCS_MODULE_SPECIFIC_CORRECTION_EN_ENABLE BIT(0)
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#define CCS_R_DYNAMIC_TRIPLET_DEFECT_CORRECT_EN CCI_REG8(0x0b13)
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#define CCS_DYNAMIC_TRIPLET_DEFECT_CORRECT_EN_ENABLE BIT(0)
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#define CCS_R_NF_CTRL CCI_REG8(0x0b15)
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#define CCS_NF_CTRL_LUMA BIT(0)
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#define CCS_NF_CTRL_CHROMA BIT(1)
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#define CCS_NF_CTRL_COMBINED BIT(2)
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#define CCS_R_OB_READOUT_CONTROL CCI_REG8(0x0b30)
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#define CCS_OB_READOUT_CONTROL_ENABLE BIT(0)
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#define CCS_OB_READOUT_CONTROL_INTERLEAVING BIT(1)
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#define CCS_R_OB_VIRTUAL_CHANNEL CCI_REG8(0x0b31)
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#define CCS_R_OB_DT CCI_REG8(0x0b32)
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#define CCS_R_OB_DATA_FORMAT CCI_REG8(0x0b33)
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#define CCS_R_COLOR_TEMPERATURE CCI_REG16(0x0b8c)
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#define CCS_R_ABSOLUTE_GAIN_GREENR CCI_REG16(0x0b8e)
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#define CCS_R_ABSOLUTE_GAIN_RED CCI_REG16(0x0b90)
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#define CCS_R_ABSOLUTE_GAIN_BLUE CCI_REG16(0x0b92)
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#define CCS_R_ABSOLUTE_GAIN_GREENB CCI_REG16(0x0b94)
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#define CCS_R_CFA_CONVERSION_CTRL CCI_REG8(0x0ba0)
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#define CCS_CFA_CONVERSION_CTRL_BAYER_CONVERSION_ENABLE BIT(0)
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#define CCS_R_FLASH_STROBE_ADJUSTMENT CCI_REG8(0x0c12)
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#define CCS_R_FLASH_STROBE_START_POINT CCI_REG16(0x0c14)
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#define CCS_R_TFLASH_STROBE_DELAY_RS_CTRL CCI_REG16(0x0c16)
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#define CCS_R_TFLASH_STROBE_WIDTH_HIGH_RS_CTRL CCI_REG16(0x0c18)
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#define CCS_R_FLASH_MODE_RS CCI_REG8(0x0c1a)
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#define CCS_FLASH_MODE_RS_CONTINUOUS BIT(0)
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#define CCS_FLASH_MODE_RS_TRUNCATE BIT(1)
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#define CCS_FLASH_MODE_RS_ASYNC BIT(3)
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#define CCS_R_FLASH_TRIGGER_RS CCI_REG8(0x0c1b)
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#define CCS_R_FLASH_STATUS CCI_REG8(0x0c1c)
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#define CCS_FLASH_STATUS_RETIMED BIT(0)
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#define CCS_R_SA_STROBE_MODE CCI_REG8(0x0c1d)
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#define CCS_SA_STROBE_MODE_CONTINUOUS BIT(0)
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#define CCS_SA_STROBE_MODE_TRUNCATE BIT(1)
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#define CCS_SA_STROBE_MODE_ASYNC BIT(3)
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#define CCS_SA_STROBE_MODE_ADJUST_EDGE BIT(4)
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#define CCS_R_SA_STROBE_START_POINT CCI_REG16(0x0c1e)
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#define CCS_R_TSA_STROBE_DELAY_CTRL CCI_REG16(0x0c20)
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#define CCS_R_TSA_STROBE_WIDTH_CTRL CCI_REG16(0x0c22)
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#define CCS_R_SA_STROBE_TRIGGER CCI_REG8(0x0c24)
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#define CCS_R_SA_STROBE_STATUS CCI_REG8(0x0c25)
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#define CCS_SA_STROBE_STATUS_RETIMED BIT(0)
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#define CCS_R_TSA_STROBE_RE_DELAY_CTRL CCI_REG16(0x0c30)
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#define CCS_R_TSA_STROBE_FE_DELAY_CTRL CCI_REG16(0x0c32)
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#define CCS_R_PDAF_CTRL CCI_REG16(0x0d00)
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#define CCS_PDAF_CTRL_ENABLE BIT(0)
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#define CCS_PDAF_CTRL_PROCESSED BIT(1)
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#define CCS_PDAF_CTRL_INTERLEAVED BIT(2)
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#define CCS_PDAF_CTRL_VISIBLE_PDAF_CORRECTION BIT(3)
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#define CCS_R_PDAF_VC CCI_REG8(0x0d02)
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#define CCS_R_PDAF_DT CCI_REG8(0x0d03)
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#define CCS_R_PD_X_ADDR_START CCI_REG16(0x0d04)
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#define CCS_R_PD_Y_ADDR_START CCI_REG16(0x0d06)
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#define CCS_R_PD_X_ADDR_END CCI_REG16(0x0d08)
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#define CCS_R_PD_Y_ADDR_END CCI_REG16(0x0d0a)
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#define CCS_R_BRACKETING_LUT_CTRL CCI_REG8(0x0e00)
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#define CCS_R_BRACKETING_LUT_MODE CCI_REG8(0x0e01)
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#define CCS_BRACKETING_LUT_MODE_CONTINUE_STREAMING BIT(0)
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#define CCS_BRACKETING_LUT_MODE_LOOP_MODE BIT(1)
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#define CCS_R_BRACKETING_LUT_ENTRY_CTRL CCI_REG8(0x0e02)
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#define CCS_R_BRACKETING_LUT_FRAME(n) CCI_REG8(0x0e10 + (n))
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#define CCS_LIM_BRACKETING_LUT_FRAME_MIN_N 0U
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#define CCS_LIM_BRACKETING_LUT_FRAME_MAX_N 239U
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#define CCS_R_INTEGRATION_TIME_CAPABILITY CCI_REG16(0x1000)
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#define CCS_INTEGRATION_TIME_CAPABILITY_FINE BIT(0)
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#define CCS_R_COARSE_INTEGRATION_TIME_MIN CCI_REG16(0x1004)
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#define CCS_R_COARSE_INTEGRATION_TIME_MAX_MARGIN CCI_REG16(0x1006)
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#define CCS_R_FINE_INTEGRATION_TIME_MIN CCI_REG16(0x1008)
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#define CCS_R_FINE_INTEGRATION_TIME_MAX_MARGIN CCI_REG16(0x100a)
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#define CCS_R_DIGITAL_GAIN_CAPABILITY CCI_REG8(0x1081)
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#define CCS_DIGITAL_GAIN_CAPABILITY_NONE 0U
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#define CCS_DIGITAL_GAIN_CAPABILITY_GLOBAL 2U
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#define CCS_R_DIGITAL_GAIN_MIN CCI_REG16(0x1084)
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#define CCS_R_DIGITAL_GAIN_MAX CCI_REG16(0x1086)
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#define CCS_R_DIGITAL_GAIN_STEP_SIZE CCI_REG16(0x1088)
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#define CCS_R_PEDESTAL_CAPABILITY CCI_REG8(0x10e0)
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#define CCS_R_ADC_CAPABILITY CCI_REG8(0x10f0)
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#define CCS_ADC_CAPABILITY_BIT_DEPTH_CTRL BIT(0)
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#define CCS_R_ADC_BIT_DEPTH_CAPABILITY CCI_REG32(0x10f4)
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#define CCS_R_MIN_EXT_CLK_FREQ_MHZ (CCI_REG32(0x1100) | CCS_FL_FLOAT_IREAL)
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#define CCS_R_MAX_EXT_CLK_FREQ_MHZ (CCI_REG32(0x1104) | CCS_FL_FLOAT_IREAL)
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#define CCS_R_MIN_PRE_PLL_CLK_DIV CCI_REG16(0x1108)
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#define CCS_R_MAX_PRE_PLL_CLK_DIV CCI_REG16(0x110a)
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#define CCS_R_MIN_PLL_IP_CLK_FREQ_MHZ (CCI_REG32(0x110c) | CCS_FL_FLOAT_IREAL)
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#define CCS_R_MAX_PLL_IP_CLK_FREQ_MHZ (CCI_REG32(0x1110) | CCS_FL_FLOAT_IREAL)
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#define CCS_R_MIN_PLL_MULTIPLIER CCI_REG16(0x1114)
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#define CCS_R_MAX_PLL_MULTIPLIER CCI_REG16(0x1116)
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#define CCS_R_MIN_PLL_OP_CLK_FREQ_MHZ (CCI_REG32(0x1118) | CCS_FL_FLOAT_IREAL)
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#define CCS_R_MAX_PLL_OP_CLK_FREQ_MHZ (CCI_REG32(0x111c) | CCS_FL_FLOAT_IREAL)
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#define CCS_R_MIN_VT_SYS_CLK_DIV CCI_REG16(0x1120)
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#define CCS_R_MAX_VT_SYS_CLK_DIV CCI_REG16(0x1122)
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#define CCS_R_MIN_VT_SYS_CLK_FREQ_MHZ (CCI_REG32(0x1124) | CCS_FL_FLOAT_IREAL)
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#define CCS_R_MAX_VT_SYS_CLK_FREQ_MHZ (CCI_REG32(0x1128) | CCS_FL_FLOAT_IREAL)
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#define CCS_R_MIN_VT_PIX_CLK_FREQ_MHZ (CCI_REG32(0x112c) | CCS_FL_FLOAT_IREAL)
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#define CCS_R_MAX_VT_PIX_CLK_FREQ_MHZ (CCI_REG32(0x1130) | CCS_FL_FLOAT_IREAL)
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#define CCS_R_MIN_VT_PIX_CLK_DIV CCI_REG16(0x1134)
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#define CCS_R_MAX_VT_PIX_CLK_DIV CCI_REG16(0x1136)
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#define CCS_R_CLOCK_CALCULATION CCI_REG8(0x1138)
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#define CCS_CLOCK_CALCULATION_LANE_SPEED BIT(0)
|
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#define CCS_CLOCK_CALCULATION_LINK_DECOUPLED BIT(1)
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#define CCS_CLOCK_CALCULATION_DUAL_PLL_OP_SYS_DDR BIT(2)
|
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#define CCS_CLOCK_CALCULATION_DUAL_PLL_OP_PIX_DDR BIT(3)
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#define CCS_R_NUM_OF_VT_LANES CCI_REG8(0x1139)
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#define CCS_R_NUM_OF_OP_LANES CCI_REG8(0x113a)
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#define CCS_R_OP_BITS_PER_LANE CCI_REG8(0x113b)
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#define CCS_R_MIN_FRAME_LENGTH_LINES CCI_REG16(0x1140)
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#define CCS_R_MAX_FRAME_LENGTH_LINES CCI_REG16(0x1142)
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#define CCS_R_MIN_LINE_LENGTH_PCK CCI_REG16(0x1144)
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#define CCS_R_MAX_LINE_LENGTH_PCK CCI_REG16(0x1146)
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#define CCS_R_MIN_LINE_BLANKING_PCK CCI_REG16(0x1148)
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#define CCS_R_MIN_FRAME_BLANKING_LINES CCI_REG16(0x114a)
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#define CCS_R_MIN_LINE_LENGTH_PCK_STEP_SIZE CCI_REG8(0x114c)
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#define CCS_R_TIMING_MODE_CAPABILITY CCI_REG8(0x114d)
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#define CCS_TIMING_MODE_CAPABILITY_AUTO_FRAME_LENGTH BIT(0)
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#define CCS_TIMING_MODE_CAPABILITY_ROLLING_SHUTTER_MANUAL_READOUT BIT(2)
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#define CCS_TIMING_MODE_CAPABILITY_DELAYED_EXPOSURE_START BIT(3)
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#define CCS_TIMING_MODE_CAPABILITY_MANUAL_EXPOSURE_EMBEDDED_DATA BIT(4)
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#define CCS_R_FRAME_MARGIN_MAX_VALUE CCI_REG16(0x114e)
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#define CCS_R_FRAME_MARGIN_MIN_VALUE CCI_REG8(0x1150)
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#define CCS_R_GAIN_DELAY_TYPE CCI_REG8(0x1151)
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#define CCS_GAIN_DELAY_TYPE_FIXED 0U
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#define CCS_GAIN_DELAY_TYPE_VARIABLE 1U
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#define CCS_R_MIN_OP_SYS_CLK_DIV CCI_REG16(0x1160)
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#define CCS_R_MAX_OP_SYS_CLK_DIV CCI_REG16(0x1162)
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#define CCS_R_MIN_OP_SYS_CLK_FREQ_MHZ (CCI_REG32(0x1164) | CCS_FL_FLOAT_IREAL)
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#define CCS_R_MAX_OP_SYS_CLK_FREQ_MHZ (CCI_REG32(0x1168) | CCS_FL_FLOAT_IREAL)
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#define CCS_R_MIN_OP_PIX_CLK_DIV CCI_REG16(0x116c)
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#define CCS_R_MAX_OP_PIX_CLK_DIV CCI_REG16(0x116e)
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#define CCS_R_MIN_OP_PIX_CLK_FREQ_MHZ (CCI_REG32(0x1170) | CCS_FL_FLOAT_IREAL)
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#define CCS_R_MAX_OP_PIX_CLK_FREQ_MHZ (CCI_REG32(0x1174) | CCS_FL_FLOAT_IREAL)
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#define CCS_R_X_ADDR_MIN CCI_REG16(0x1180)
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#define CCS_R_Y_ADDR_MIN CCI_REG16(0x1182)
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#define CCS_R_X_ADDR_MAX CCI_REG16(0x1184)
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#define CCS_R_Y_ADDR_MAX CCI_REG16(0x1186)
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#define CCS_R_MIN_X_OUTPUT_SIZE CCI_REG16(0x1188)
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#define CCS_R_MIN_Y_OUTPUT_SIZE CCI_REG16(0x118a)
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#define CCS_R_MAX_X_OUTPUT_SIZE CCI_REG16(0x118c)
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#define CCS_R_MAX_Y_OUTPUT_SIZE CCI_REG16(0x118e)
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#define CCS_R_X_ADDR_START_DIV_CONSTANT CCI_REG8(0x1190)
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#define CCS_R_Y_ADDR_START_DIV_CONSTANT CCI_REG8(0x1191)
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#define CCS_R_X_ADDR_END_DIV_CONSTANT CCI_REG8(0x1192)
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#define CCS_R_Y_ADDR_END_DIV_CONSTANT CCI_REG8(0x1193)
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#define CCS_R_X_SIZE_DIV CCI_REG8(0x1194)
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#define CCS_R_Y_SIZE_DIV CCI_REG8(0x1195)
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#define CCS_R_X_OUTPUT_DIV CCI_REG8(0x1196)
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#define CCS_R_Y_OUTPUT_DIV CCI_REG8(0x1197)
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#define CCS_R_NON_FLEXIBLE_RESOLUTION_SUPPORT CCI_REG8(0x1198)
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#define CCS_NON_FLEXIBLE_RESOLUTION_SUPPORT_NEW_PIX_ADDR BIT(0)
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#define CCS_NON_FLEXIBLE_RESOLUTION_SUPPORT_NEW_OUTPUT_RES BIT(1)
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#define CCS_NON_FLEXIBLE_RESOLUTION_SUPPORT_OUTPUT_CROP_NO_PAD BIT(2)
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#define CCS_NON_FLEXIBLE_RESOLUTION_SUPPORT_OUTPUT_SIZE_LANE_DEP BIT(3)
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#define CCS_R_MIN_OP_PRE_PLL_CLK_DIV CCI_REG16(0x11a0)
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#define CCS_R_MAX_OP_PRE_PLL_CLK_DIV CCI_REG16(0x11a2)
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#define CCS_R_MIN_OP_PLL_IP_CLK_FREQ_MHZ (CCI_REG32(0x11a4) | CCS_FL_FLOAT_IREAL)
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#define CCS_R_MAX_OP_PLL_IP_CLK_FREQ_MHZ (CCI_REG32(0x11a8) | CCS_FL_FLOAT_IREAL)
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#define CCS_R_MIN_OP_PLL_MULTIPLIER CCI_REG16(0x11ac)
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#define CCS_R_MAX_OP_PLL_MULTIPLIER CCI_REG16(0x11ae)
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#define CCS_R_MIN_OP_PLL_OP_CLK_FREQ_MHZ (CCI_REG32(0x11b0) | CCS_FL_FLOAT_IREAL)
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#define CCS_R_MAX_OP_PLL_OP_CLK_FREQ_MHZ (CCI_REG32(0x11b4) | CCS_FL_FLOAT_IREAL)
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#define CCS_R_CLOCK_TREE_PLL_CAPABILITY CCI_REG8(0x11b8)
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#define CCS_CLOCK_TREE_PLL_CAPABILITY_DUAL_PLL BIT(0)
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#define CCS_CLOCK_TREE_PLL_CAPABILITY_SINGLE_PLL BIT(1)
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#define CCS_CLOCK_TREE_PLL_CAPABILITY_EXT_DIVIDER BIT(2)
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#define CCS_CLOCK_TREE_PLL_CAPABILITY_FLEXIBLE_OP_PIX_CLK_DIV BIT(3)
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#define CCS_R_CLOCK_CAPA_TYPE_CAPABILITY CCI_REG8(0x11b9)
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#define CCS_CLOCK_CAPA_TYPE_CAPABILITY_IREAL BIT(0)
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#define CCS_R_MIN_EVEN_INC CCI_REG16(0x11c0)
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#define CCS_R_MIN_ODD_INC CCI_REG16(0x11c2)
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#define CCS_R_MAX_EVEN_INC CCI_REG16(0x11c4)
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#define CCS_R_MAX_ODD_INC CCI_REG16(0x11c6)
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#define CCS_R_AUX_SUBSAMP_CAPABILITY CCI_REG8(0x11c8)
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#define CCS_AUX_SUBSAMP_CAPABILITY_FACTOR_POWER_OF_2 BIT(1)
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#define CCS_R_AUX_SUBSAMP_MONO_CAPABILITY CCI_REG8(0x11c9)
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#define CCS_AUX_SUBSAMP_MONO_CAPABILITY_FACTOR_POWER_OF_2 BIT(1)
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#define CCS_R_MONOCHROME_CAPABILITY CCI_REG8(0x11ca)
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#define CCS_MONOCHROME_CAPABILITY_INC_ODD 0U
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#define CCS_MONOCHROME_CAPABILITY_INC_EVEN 1U
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#define CCS_R_PIXEL_READOUT_CAPABILITY CCI_REG8(0x11cb)
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#define CCS_PIXEL_READOUT_CAPABILITY_BAYER 0U
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#define CCS_PIXEL_READOUT_CAPABILITY_MONOCHROME 1U
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#define CCS_PIXEL_READOUT_CAPABILITY_BAYER_AND_MONO 2U
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#define CCS_R_MIN_EVEN_INC_MONO CCI_REG16(0x11cc)
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#define CCS_R_MAX_EVEN_INC_MONO CCI_REG16(0x11ce)
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#define CCS_R_MIN_ODD_INC_MONO CCI_REG16(0x11d0)
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#define CCS_R_MAX_ODD_INC_MONO CCI_REG16(0x11d2)
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#define CCS_R_MIN_EVEN_INC_BC2 CCI_REG16(0x11d4)
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#define CCS_R_MAX_EVEN_INC_BC2 CCI_REG16(0x11d6)
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#define CCS_R_MIN_ODD_INC_BC2 CCI_REG16(0x11d8)
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#define CCS_R_MAX_ODD_INC_BC2 CCI_REG16(0x11da)
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#define CCS_R_MIN_EVEN_INC_MONO_BC2 CCI_REG16(0x11dc)
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#define CCS_R_MAX_EVEN_INC_MONO_BC2 CCI_REG16(0x11de)
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#define CCS_R_MIN_ODD_INC_MONO_BC2 CCI_REG16(0x11f0)
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#define CCS_R_MAX_ODD_INC_MONO_BC2 CCI_REG16(0x11f2)
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#define CCS_R_SCALING_CAPABILITY CCI_REG16(0x1200)
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#define CCS_SCALING_CAPABILITY_NONE 0U
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#define CCS_SCALING_CAPABILITY_HORIZONTAL 1U
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#define CCS_SCALING_CAPABILITY_RESERVED 2U
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#define CCS_R_SCALER_M_MIN CCI_REG16(0x1204)
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#define CCS_R_SCALER_M_MAX CCI_REG16(0x1206)
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#define CCS_R_SCALER_N_MIN CCI_REG16(0x1208)
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#define CCS_R_SCALER_N_MAX CCI_REG16(0x120a)
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#define CCS_R_DIGITAL_CROP_CAPABILITY CCI_REG8(0x120e)
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#define CCS_DIGITAL_CROP_CAPABILITY_NONE 0U
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#define CCS_DIGITAL_CROP_CAPABILITY_INPUT_CROP 1U
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#define CCS_R_HDR_CAPABILITY_1 CCI_REG8(0x1210)
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#define CCS_HDR_CAPABILITY_1_2X2_BINNING BIT(0)
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#define CCS_HDR_CAPABILITY_1_COMBINED_ANALOG_GAIN BIT(1)
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#define CCS_HDR_CAPABILITY_1_SEPARATE_ANALOG_GAIN BIT(2)
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#define CCS_HDR_CAPABILITY_1_UPSCALING BIT(3)
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#define CCS_HDR_CAPABILITY_1_RESET_SYNC BIT(4)
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#define CCS_HDR_CAPABILITY_1_DIRECT_SHORT_EXP_TIMING BIT(5)
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#define CCS_HDR_CAPABILITY_1_DIRECT_SHORT_EXP_SYNTHESIS BIT(6)
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#define CCS_R_MIN_HDR_BIT_DEPTH CCI_REG8(0x1211)
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#define CCS_R_HDR_RESOLUTION_SUB_TYPES CCI_REG8(0x1212)
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#define CCS_R_HDR_RESOLUTION_SUB_TYPE(n) CCI_REG8(0x1213 + (n))
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#define CCS_LIM_HDR_RESOLUTION_SUB_TYPE_MIN_N 0U
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#define CCS_LIM_HDR_RESOLUTION_SUB_TYPE_MAX_N 1U
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#define CCS_HDR_RESOLUTION_SUB_TYPE_ROW_SHIFT 0U
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#define CCS_HDR_RESOLUTION_SUB_TYPE_ROW_MASK 0xf
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#define CCS_HDR_RESOLUTION_SUB_TYPE_COLUMN_SHIFT 4U
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#define CCS_HDR_RESOLUTION_SUB_TYPE_COLUMN_MASK 0xf0
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#define CCS_R_HDR_CAPABILITY_2 CCI_REG8(0x121b)
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#define CCS_HDR_CAPABILITY_2_COMBINED_DIGITAL_GAIN BIT(0)
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#define CCS_HDR_CAPABILITY_2_SEPARATE_DIGITAL_GAIN BIT(1)
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#define CCS_HDR_CAPABILITY_2_TIMING_MODE BIT(3)
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#define CCS_HDR_CAPABILITY_2_SYNTHESIS_MODE BIT(4)
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#define CCS_R_MAX_HDR_BIT_DEPTH CCI_REG8(0x121c)
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#define CCS_R_USL_SUPPORT_CAPABILITY CCI_REG8(0x1230)
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#define CCS_USL_SUPPORT_CAPABILITY_CLOCK_TREE BIT(0)
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#define CCS_USL_SUPPORT_CAPABILITY_REV_CLOCK_TREE BIT(1)
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#define CCS_USL_SUPPORT_CAPABILITY_REV_CLOCK_CALC BIT(2)
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#define CCS_R_USL_CLOCK_MODE_D_CAPABILITY CCI_REG8(0x1231)
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#define CCS_USL_CLOCK_MODE_D_CAPABILITY_CONT_CLOCK_STANDBY BIT(0)
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#define CCS_USL_CLOCK_MODE_D_CAPABILITY_CONT_CLOCK_VBLANK BIT(1)
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#define CCS_USL_CLOCK_MODE_D_CAPABILITY_CONT_CLOCK_HBLANK BIT(2)
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#define CCS_USL_CLOCK_MODE_D_CAPABILITY_NONCONT_CLOCK_STANDBY BIT(3)
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#define CCS_USL_CLOCK_MODE_D_CAPABILITY_NONCONT_CLOCK_VBLANK BIT(4)
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#define CCS_USL_CLOCK_MODE_D_CAPABILITY_NONCONT_CLOCK_HBLANK BIT(5)
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#define CCS_R_MIN_OP_SYS_CLK_DIV_REV CCI_REG8(0x1234)
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#define CCS_R_MAX_OP_SYS_CLK_DIV_REV CCI_REG8(0x1236)
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#define CCS_R_MIN_OP_PIX_CLK_DIV_REV CCI_REG8(0x1238)
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#define CCS_R_MAX_OP_PIX_CLK_DIV_REV CCI_REG8(0x123a)
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#define CCS_R_MIN_OP_SYS_CLK_FREQ_REV_MHZ (CCI_REG32(0x123c) | CCS_FL_FLOAT_IREAL)
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#define CCS_R_MAX_OP_SYS_CLK_FREQ_REV_MHZ (CCI_REG32(0x1240) | CCS_FL_FLOAT_IREAL)
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#define CCS_R_MIN_OP_PIX_CLK_FREQ_REV_MHZ (CCI_REG32(0x1244) | CCS_FL_FLOAT_IREAL)
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#define CCS_R_MAX_OP_PIX_CLK_FREQ_REV_MHZ (CCI_REG32(0x1248) | CCS_FL_FLOAT_IREAL)
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#define CCS_R_MAX_BITRATE_REV_D_MODE_MBPS (CCI_REG32(0x124c) | CCS_FL_IREAL)
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#define CCS_R_MAX_SYMRATE_REV_C_MODE_MSPS (CCI_REG32(0x1250) | CCS_FL_IREAL)
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#define CCS_R_COMPRESSION_CAPABILITY CCI_REG8(0x1300)
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#define CCS_COMPRESSION_CAPABILITY_DPCM_PCM_SIMPLE BIT(0)
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#define CCS_R_TEST_MODE_CAPABILITY CCI_REG16(0x1310)
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#define CCS_TEST_MODE_CAPABILITY_SOLID_COLOR BIT(0)
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#define CCS_TEST_MODE_CAPABILITY_COLOR_BARS BIT(1)
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#define CCS_TEST_MODE_CAPABILITY_FADE_TO_GREY BIT(2)
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#define CCS_TEST_MODE_CAPABILITY_PN9 BIT(3)
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#define CCS_TEST_MODE_CAPABILITY_COLOR_TILE BIT(5)
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#define CCS_R_PN9_DATA_FORMAT1 CCI_REG8(0x1312)
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#define CCS_R_PN9_DATA_FORMAT2 CCI_REG8(0x1313)
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#define CCS_R_PN9_DATA_FORMAT3 CCI_REG8(0x1314)
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#define CCS_R_PN9_DATA_FORMAT4 CCI_REG8(0x1315)
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#define CCS_R_PN9_MISC_CAPABILITY CCI_REG8(0x1316)
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#define CCS_PN9_MISC_CAPABILITY_NUM_PIXELS_SHIFT 0U
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#define CCS_PN9_MISC_CAPABILITY_NUM_PIXELS_MASK 0x7
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#define CCS_PN9_MISC_CAPABILITY_COMPRESSION BIT(3)
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#define CCS_R_TEST_PATTERN_CAPABILITY CCI_REG8(0x1317)
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#define CCS_TEST_PATTERN_CAPABILITY_NO_REPEAT BIT(1)
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#define CCS_R_PATTERN_SIZE_DIV_M1 CCI_REG8(0x1318)
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#define CCS_R_FIFO_SUPPORT_CAPABILITY CCI_REG8(0x1502)
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#define CCS_FIFO_SUPPORT_CAPABILITY_NONE 0U
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#define CCS_FIFO_SUPPORT_CAPABILITY_DERATING 1U
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#define CCS_FIFO_SUPPORT_CAPABILITY_DERATING_OVERRATING 2U
|
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#define CCS_R_PHY_CTRL_CAPABILITY CCI_REG8(0x1600)
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#define CCS_PHY_CTRL_CAPABILITY_AUTO_PHY_CTL BIT(0)
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#define CCS_PHY_CTRL_CAPABILITY_UI_PHY_CTL BIT(1)
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#define CCS_PHY_CTRL_CAPABILITY_DPHY_TIME_UI_REG_1_CTL BIT(2)
|
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#define CCS_PHY_CTRL_CAPABILITY_DPHY_TIME_UI_REG_2_CTL BIT(3)
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#define CCS_PHY_CTRL_CAPABILITY_DPHY_TIME_CTL BIT(4)
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#define CCS_PHY_CTRL_CAPABILITY_DPHY_EXT_TIME_UI_REG_1_CTL BIT(5)
|
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#define CCS_PHY_CTRL_CAPABILITY_DPHY_EXT_TIME_UI_REG_2_CTL BIT(6)
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#define CCS_PHY_CTRL_CAPABILITY_DPHY_EXT_TIME_CTL BIT(7)
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#define CCS_R_CSI_DPHY_LANE_MODE_CAPABILITY CCI_REG8(0x1601)
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#define CCS_CSI_DPHY_LANE_MODE_CAPABILITY_1_LANE BIT(0)
|
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#define CCS_CSI_DPHY_LANE_MODE_CAPABILITY_2_LANE BIT(1)
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#define CCS_CSI_DPHY_LANE_MODE_CAPABILITY_3_LANE BIT(2)
|
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#define CCS_CSI_DPHY_LANE_MODE_CAPABILITY_4_LANE BIT(3)
|
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#define CCS_CSI_DPHY_LANE_MODE_CAPABILITY_5_LANE BIT(4)
|
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#define CCS_CSI_DPHY_LANE_MODE_CAPABILITY_6_LANE BIT(5)
|
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#define CCS_CSI_DPHY_LANE_MODE_CAPABILITY_7_LANE BIT(6)
|
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#define CCS_CSI_DPHY_LANE_MODE_CAPABILITY_8_LANE BIT(7)
|
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#define CCS_R_CSI_SIGNALING_MODE_CAPABILITY CCI_REG8(0x1602)
|
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#define CCS_CSI_SIGNALING_MODE_CAPABILITY_CSI_DPHY BIT(2)
|
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#define CCS_CSI_SIGNALING_MODE_CAPABILITY_CSI_CPHY BIT(3)
|
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#define CCS_R_FAST_STANDBY_CAPABILITY CCI_REG8(0x1603)
|
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#define CCS_FAST_STANDBY_CAPABILITY_NO_FRAME_TRUNCATION 0U
|
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#define CCS_FAST_STANDBY_CAPABILITY_FRAME_TRUNCATION 1U
|
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#define CCS_R_CSI_ADDRESS_CONTROL_CAPABILITY CCI_REG8(0x1604)
|
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#define CCS_CSI_ADDRESS_CONTROL_CAPABILITY_CCI_ADDR_CHANGE BIT(0)
|
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#define CCS_CSI_ADDRESS_CONTROL_CAPABILITY_2ND_CCI_ADDR BIT(1)
|
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#define CCS_CSI_ADDRESS_CONTROL_CAPABILITY_SW_CHANGEABLE_2ND_CCI_ADDR BIT(2)
|
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#define CCS_R_DATA_TYPE_CAPABILITY CCI_REG8(0x1605)
|
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#define CCS_DATA_TYPE_CAPABILITY_DPCM_PROGRAMMABLE BIT(0)
|
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#define CCS_DATA_TYPE_CAPABILITY_BOTTOM_EMBEDDED_DT_PROGRAMMABLE BIT(1)
|
|
#define CCS_DATA_TYPE_CAPABILITY_BOTTOM_EMBEDDED_VC_PROGRAMMABLE BIT(2)
|
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#define CCS_DATA_TYPE_CAPABILITY_EXT_VC_RANGE BIT(3)
|
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#define CCS_R_CSI_CPHY_LANE_MODE_CAPABILITY CCI_REG8(0x1606)
|
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#define CCS_CSI_CPHY_LANE_MODE_CAPABILITY_1_LANE BIT(0)
|
|
#define CCS_CSI_CPHY_LANE_MODE_CAPABILITY_2_LANE BIT(1)
|
|
#define CCS_CSI_CPHY_LANE_MODE_CAPABILITY_3_LANE BIT(2)
|
|
#define CCS_CSI_CPHY_LANE_MODE_CAPABILITY_4_LANE BIT(3)
|
|
#define CCS_CSI_CPHY_LANE_MODE_CAPABILITY_5_LANE BIT(4)
|
|
#define CCS_CSI_CPHY_LANE_MODE_CAPABILITY_6_LANE BIT(5)
|
|
#define CCS_CSI_CPHY_LANE_MODE_CAPABILITY_7_LANE BIT(6)
|
|
#define CCS_CSI_CPHY_LANE_MODE_CAPABILITY_8_LANE BIT(7)
|
|
#define CCS_R_EMB_DATA_CAPABILITY CCI_REG8(0x1607)
|
|
#define CCS_EMB_DATA_CAPABILITY_TWO_BYTES_PER_RAW16 BIT(0)
|
|
#define CCS_EMB_DATA_CAPABILITY_TWO_BYTES_PER_RAW20 BIT(1)
|
|
#define CCS_EMB_DATA_CAPABILITY_TWO_BYTES_PER_RAW24 BIT(2)
|
|
#define CCS_EMB_DATA_CAPABILITY_NO_ONE_BYTE_PER_RAW16 BIT(3)
|
|
#define CCS_EMB_DATA_CAPABILITY_NO_ONE_BYTE_PER_RAW20 BIT(4)
|
|
#define CCS_EMB_DATA_CAPABILITY_NO_ONE_BYTE_PER_RAW24 BIT(5)
|
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#define CCS_R_MAX_PER_LANE_BITRATE_LANE_D_MODE_MBPS(n) (CCI_REG32(0x1608 + ((n) < 4 ? (n) * 4 : 0x32 + ((n) - 4) * 4)) | CCS_FL_IREAL)
|
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#define CCS_LIM_MAX_PER_LANE_BITRATE_LANE_D_MODE_MBPS_MIN_N 0U
|
|
#define CCS_LIM_MAX_PER_LANE_BITRATE_LANE_D_MODE_MBPS_MAX_N 7U
|
|
#define CCS_R_TEMP_SENSOR_CAPABILITY CCI_REG8(0x1618)
|
|
#define CCS_TEMP_SENSOR_CAPABILITY_SUPPORTED BIT(0)
|
|
#define CCS_TEMP_SENSOR_CAPABILITY_CCS_FORMAT BIT(1)
|
|
#define CCS_TEMP_SENSOR_CAPABILITY_RESET_0X80 BIT(2)
|
|
#define CCS_R_MAX_PER_LANE_BITRATE_LANE_C_MODE_MBPS(n) (CCI_REG32(0x161a + ((n) < 4 ? (n) * 4 : 0x30 + ((n) - 4) * 4)) | CCS_FL_IREAL)
|
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#define CCS_LIM_MAX_PER_LANE_BITRATE_LANE_C_MODE_MBPS_MIN_N 0U
|
|
#define CCS_LIM_MAX_PER_LANE_BITRATE_LANE_C_MODE_MBPS_MAX_N 7U
|
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#define CCS_R_DPHY_EQUALIZATION_CAPABILITY CCI_REG8(0x162b)
|
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#define CCS_DPHY_EQUALIZATION_CAPABILITY_EQUALIZATION_CTRL BIT(0)
|
|
#define CCS_DPHY_EQUALIZATION_CAPABILITY_EQ1 BIT(1)
|
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#define CCS_DPHY_EQUALIZATION_CAPABILITY_EQ2 BIT(2)
|
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#define CCS_R_CPHY_EQUALIZATION_CAPABILITY CCI_REG8(0x162c)
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#define CCS_CPHY_EQUALIZATION_CAPABILITY_EQUALIZATION_CTRL BIT(0)
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#define CCS_R_DPHY_PREAMBLE_CAPABILITY CCI_REG8(0x162d)
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#define CCS_DPHY_PREAMBLE_CAPABILITY_PREAMBLE_SEQ_CTRL BIT(0)
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#define CCS_R_DPHY_SSC_CAPABILITY CCI_REG8(0x162e)
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#define CCS_DPHY_SSC_CAPABILITY_SUPPORTED BIT(0)
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#define CCS_R_CPHY_CALIBRATION_CAPABILITY CCI_REG8(0x162f)
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#define CCS_CPHY_CALIBRATION_CAPABILITY_MANUAL BIT(0)
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#define CCS_CPHY_CALIBRATION_CAPABILITY_MANUAL_STREAMING BIT(1)
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#define CCS_CPHY_CALIBRATION_CAPABILITY_FORMAT_1_CTRL BIT(2)
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#define CCS_CPHY_CALIBRATION_CAPABILITY_FORMAT_2_CTRL BIT(3)
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#define CCS_CPHY_CALIBRATION_CAPABILITY_FORMAT_3_CTRL BIT(4)
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#define CCS_R_DPHY_CALIBRATION_CAPABILITY CCI_REG8(0x1630)
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#define CCS_DPHY_CALIBRATION_CAPABILITY_MANUAL BIT(0)
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#define CCS_DPHY_CALIBRATION_CAPABILITY_MANUAL_STREAMING BIT(1)
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#define CCS_DPHY_CALIBRATION_CAPABILITY_ALTERNATE_SEQ BIT(2)
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#define CCS_R_PHY_CTRL_CAPABILITY_2 CCI_REG8(0x1631)
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#define CCS_PHY_CTRL_CAPABILITY_2_TGR_LENGTH BIT(0)
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#define CCS_PHY_CTRL_CAPABILITY_2_TGR_PREAMBLE_PROG_SEQ BIT(1)
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#define CCS_PHY_CTRL_CAPABILITY_2_EXTRA_CPHY_MANUAL_TIMING BIT(2)
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#define CCS_PHY_CTRL_CAPABILITY_2_CLOCK_BASED_MANUAL_CDPHY BIT(3)
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#define CCS_PHY_CTRL_CAPABILITY_2_CLOCK_BASED_MANUAL_DPHY BIT(4)
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#define CCS_PHY_CTRL_CAPABILITY_2_CLOCK_BASED_MANUAL_CPHY BIT(5)
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#define CCS_PHY_CTRL_CAPABILITY_2_MANUAL_LP_DPHY BIT(6)
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#define CCS_PHY_CTRL_CAPABILITY_2_MANUAL_LP_CPHY BIT(7)
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#define CCS_R_LRTE_CPHY_CAPABILITY CCI_REG8(0x1632)
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#define CCS_LRTE_CPHY_CAPABILITY_PDQ_SHORT BIT(0)
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#define CCS_LRTE_CPHY_CAPABILITY_SPACER_SHORT BIT(1)
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#define CCS_LRTE_CPHY_CAPABILITY_PDQ_LONG BIT(2)
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#define CCS_LRTE_CPHY_CAPABILITY_SPACER_LONG BIT(3)
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#define CCS_LRTE_CPHY_CAPABILITY_SPACER_NO_PDQ BIT(4)
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#define CCS_R_LRTE_DPHY_CAPABILITY CCI_REG8(0x1633)
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#define CCS_LRTE_DPHY_CAPABILITY_PDQ_SHORT_OPT1 BIT(0)
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#define CCS_LRTE_DPHY_CAPABILITY_SPACER_SHORT_OPT1 BIT(1)
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#define CCS_LRTE_DPHY_CAPABILITY_PDQ_LONG_OPT1 BIT(2)
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#define CCS_LRTE_DPHY_CAPABILITY_SPACER_LONG_OPT1 BIT(3)
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#define CCS_LRTE_DPHY_CAPABILITY_SPACER_SHORT_OPT2 BIT(4)
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#define CCS_LRTE_DPHY_CAPABILITY_SPACER_LONG_OPT2 BIT(5)
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#define CCS_LRTE_DPHY_CAPABILITY_SPACER_NO_PDQ_OPT1 BIT(6)
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#define CCS_LRTE_DPHY_CAPABILITY_SPACER_VARIABLE_OPT2 BIT(7)
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#define CCS_R_ALPS_CAPABILITY_DPHY CCI_REG8(0x1634)
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#define CCS_ALPS_CAPABILITY_DPHY_LVLP_NOT_SUPPORTED 0U
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#define CCS_ALPS_CAPABILITY_DPHY_LVLP_SUPPORTED 1U
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#define CCS_ALPS_CAPABILITY_DPHY_CONTROLLABLE_LVLP 2U
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#define CCS_R_ALPS_CAPABILITY_CPHY CCI_REG8(0x1635)
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#define CCS_ALPS_CAPABILITY_CPHY_LVLP_NOT_SUPPORTED 0U
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#define CCS_ALPS_CAPABILITY_CPHY_LVLP_SUPPORTED 1U
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#define CCS_ALPS_CAPABILITY_CPHY_CONTROLLABLE_LVLP 2U
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#define CCS_ALPS_CAPABILITY_CPHY_ALP_NOT_SUPPORTED 0xc
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#define CCS_ALPS_CAPABILITY_CPHY_ALP_SUPPORTED 0xd
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#define CCS_ALPS_CAPABILITY_CPHY_CONTROLLABLE_ALP 0xe
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#define CCS_R_SCRAMBLING_CAPABILITY CCI_REG8(0x1636)
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#define CCS_SCRAMBLING_CAPABILITY_SCRAMBLING_SUPPORTED BIT(0)
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#define CCS_SCRAMBLING_CAPABILITY_MAX_SEEDS_PER_LANE_C_SHIFT 1U
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#define CCS_SCRAMBLING_CAPABILITY_MAX_SEEDS_PER_LANE_C_MASK 0x6
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#define CCS_SCRAMBLING_CAPABILITY_MAX_SEEDS_PER_LANE_C_1 0U
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#define CCS_SCRAMBLING_CAPABILITY_MAX_SEEDS_PER_LANE_C_4 3U
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#define CCS_SCRAMBLING_CAPABILITY_NUM_SEED_REGS_SHIFT 3U
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#define CCS_SCRAMBLING_CAPABILITY_NUM_SEED_REGS_MASK 0x38
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#define CCS_SCRAMBLING_CAPABILITY_NUM_SEED_REGS_0 0U
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#define CCS_SCRAMBLING_CAPABILITY_NUM_SEED_REGS_1 1U
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#define CCS_SCRAMBLING_CAPABILITY_NUM_SEED_REGS_4 4U
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#define CCS_SCRAMBLING_CAPABILITY_NUM_SEED_PER_LANE BIT(6)
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#define CCS_R_DPHY_MANUAL_CONSTANT CCI_REG8(0x1637)
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#define CCS_R_CPHY_MANUAL_CONSTANT CCI_REG8(0x1638)
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#define CCS_R_CSI2_INTERFACE_CAPABILITY_MISC CCI_REG8(0x1639)
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#define CCS_CSI2_INTERFACE_CAPABILITY_MISC_EOTP_SHORT_PKT_OPT2 BIT(0)
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#define CCS_R_PHY_CTRL_CAPABILITY_3 CCI_REG8(0x165c)
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#define CCS_PHY_CTRL_CAPABILITY_3_DPHY_TIMING_NOT_MULTIPLE BIT(0)
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#define CCS_PHY_CTRL_CAPABILITY_3_DPHY_MIN_TIMING_VALUE_1 BIT(1)
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#define CCS_PHY_CTRL_CAPABILITY_3_TWAKEUP_SUPPORTED BIT(2)
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#define CCS_PHY_CTRL_CAPABILITY_3_TINIT_SUPPORTED BIT(3)
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#define CCS_PHY_CTRL_CAPABILITY_3_THS_EXIT_SUPPORTED BIT(4)
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#define CCS_PHY_CTRL_CAPABILITY_3_CPHY_TIMING_NOT_MULTIPLE BIT(5)
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#define CCS_PHY_CTRL_CAPABILITY_3_CPHY_MIN_TIMING_VALUE_1 BIT(6)
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#define CCS_R_DPHY_SF CCI_REG8(0x165d)
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#define CCS_R_CPHY_SF CCI_REG8(0x165e)
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#define CCS_CPHY_SF_TWAKEUP_SHIFT 0U
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#define CCS_CPHY_SF_TWAKEUP_MASK 0xf
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#define CCS_CPHY_SF_TINIT_SHIFT 4U
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#define CCS_CPHY_SF_TINIT_MASK 0xf0
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#define CCS_R_DPHY_LIMITS_1 CCI_REG8(0x165f)
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#define CCS_DPHY_LIMITS_1_THS_PREPARE_SHIFT 0U
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#define CCS_DPHY_LIMITS_1_THS_PREPARE_MASK 0xf
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#define CCS_DPHY_LIMITS_1_THS_ZERO_SHIFT 4U
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#define CCS_DPHY_LIMITS_1_THS_ZERO_MASK 0xf0
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#define CCS_R_DPHY_LIMITS_2 CCI_REG8(0x1660)
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#define CCS_DPHY_LIMITS_2_THS_TRAIL_SHIFT 0U
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#define CCS_DPHY_LIMITS_2_THS_TRAIL_MASK 0xf
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#define CCS_DPHY_LIMITS_2_TCLK_TRAIL_MIN_SHIFT 4U
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#define CCS_DPHY_LIMITS_2_TCLK_TRAIL_MIN_MASK 0xf0
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#define CCS_R_DPHY_LIMITS_3 CCI_REG8(0x1661)
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#define CCS_DPHY_LIMITS_3_TCLK_PREPARE_SHIFT 0U
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#define CCS_DPHY_LIMITS_3_TCLK_PREPARE_MASK 0xf
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#define CCS_DPHY_LIMITS_3_TCLK_ZERO_SHIFT 4U
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#define CCS_DPHY_LIMITS_3_TCLK_ZERO_MASK 0xf0
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#define CCS_R_DPHY_LIMITS_4 CCI_REG8(0x1662)
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#define CCS_DPHY_LIMITS_4_TCLK_POST_SHIFT 0U
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#define CCS_DPHY_LIMITS_4_TCLK_POST_MASK 0xf
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#define CCS_DPHY_LIMITS_4_TLPX_SHIFT 4U
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#define CCS_DPHY_LIMITS_4_TLPX_MASK 0xf0
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#define CCS_R_DPHY_LIMITS_5 CCI_REG8(0x1663)
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#define CCS_DPHY_LIMITS_5_THS_EXIT_SHIFT 0U
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#define CCS_DPHY_LIMITS_5_THS_EXIT_MASK 0xf
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#define CCS_DPHY_LIMITS_5_TWAKEUP_SHIFT 4U
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#define CCS_DPHY_LIMITS_5_TWAKEUP_MASK 0xf0
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#define CCS_R_DPHY_LIMITS_6 CCI_REG8(0x1664)
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#define CCS_DPHY_LIMITS_6_TINIT_SHIFT 0U
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#define CCS_DPHY_LIMITS_6_TINIT_MASK 0xf
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#define CCS_R_CPHY_LIMITS_1 CCI_REG8(0x1665)
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#define CCS_CPHY_LIMITS_1_T3_PREPARE_MAX_SHIFT 0U
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#define CCS_CPHY_LIMITS_1_T3_PREPARE_MAX_MASK 0xf
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#define CCS_CPHY_LIMITS_1_T3_LPX_MAX_SHIFT 4U
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#define CCS_CPHY_LIMITS_1_T3_LPX_MAX_MASK 0xf0
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#define CCS_R_CPHY_LIMITS_2 CCI_REG8(0x1666)
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#define CCS_CPHY_LIMITS_2_THS_EXIT_MAX_SHIFT 0U
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#define CCS_CPHY_LIMITS_2_THS_EXIT_MAX_MASK 0xf
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#define CCS_CPHY_LIMITS_2_TWAKEUP_MAX_SHIFT 4U
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#define CCS_CPHY_LIMITS_2_TWAKEUP_MAX_MASK 0xf0
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#define CCS_R_CPHY_LIMITS_3 CCI_REG8(0x1667)
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#define CCS_CPHY_LIMITS_3_TINIT_MAX_SHIFT 0U
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#define CCS_CPHY_LIMITS_3_TINIT_MAX_MASK 0xf
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#define CCS_R_MIN_FRAME_LENGTH_LINES_BIN CCI_REG16(0x1700)
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#define CCS_R_MAX_FRAME_LENGTH_LINES_BIN CCI_REG16(0x1702)
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#define CCS_R_MIN_LINE_LENGTH_PCK_BIN CCI_REG16(0x1704)
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#define CCS_R_MAX_LINE_LENGTH_PCK_BIN CCI_REG16(0x1706)
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#define CCS_R_MIN_LINE_BLANKING_PCK_BIN CCI_REG16(0x1708)
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#define CCS_R_FINE_INTEGRATION_TIME_MIN_BIN CCI_REG16(0x170a)
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#define CCS_R_FINE_INTEGRATION_TIME_MAX_MARGIN_BIN CCI_REG16(0x170c)
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#define CCS_R_BINNING_CAPABILITY CCI_REG8(0x1710)
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#define CCS_BINNING_CAPABILITY_UNSUPPORTED 0U
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#define CCS_BINNING_CAPABILITY_BINNING_THEN_SUBSAMPLING 1U
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#define CCS_BINNING_CAPABILITY_SUBSAMPLING_THEN_BINNING 2U
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#define CCS_R_BINNING_WEIGHTING_CAPABILITY CCI_REG8(0x1711)
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#define CCS_BINNING_WEIGHTING_CAPABILITY_AVERAGED BIT(0)
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#define CCS_BINNING_WEIGHTING_CAPABILITY_SUMMED BIT(1)
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#define CCS_BINNING_WEIGHTING_CAPABILITY_BAYER_CORRECTED BIT(2)
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#define CCS_BINNING_WEIGHTING_CAPABILITY_MODULE_SPECIFIC_WEIGHT BIT(3)
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#define CCS_R_BINNING_SUB_TYPES CCI_REG8(0x1712)
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#define CCS_R_BINNING_SUB_TYPE(n) CCI_REG8(0x1713 + (n))
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#define CCS_LIM_BINNING_SUB_TYPE_MIN_N 0U
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#define CCS_LIM_BINNING_SUB_TYPE_MAX_N 63U
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#define CCS_BINNING_SUB_TYPE_ROW_SHIFT 0U
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#define CCS_BINNING_SUB_TYPE_ROW_MASK 0xf
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#define CCS_BINNING_SUB_TYPE_COLUMN_SHIFT 4U
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#define CCS_BINNING_SUB_TYPE_COLUMN_MASK 0xf0
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#define CCS_R_BINNING_WEIGHTING_MONO_CAPABILITY CCI_REG8(0x1771)
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#define CCS_BINNING_WEIGHTING_MONO_CAPABILITY_AVERAGED BIT(0)
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#define CCS_BINNING_WEIGHTING_MONO_CAPABILITY_SUMMED BIT(1)
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#define CCS_BINNING_WEIGHTING_MONO_CAPABILITY_BAYER_CORRECTED BIT(2)
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#define CCS_BINNING_WEIGHTING_MONO_CAPABILITY_MODULE_SPECIFIC_WEIGHT BIT(3)
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#define CCS_R_BINNING_SUB_TYPES_MONO CCI_REG8(0x1772)
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#define CCS_R_BINNING_SUB_TYPE_MONO(n) CCI_REG8(0x1773 + (n))
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#define CCS_LIM_BINNING_SUB_TYPE_MONO_MIN_N 0U
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#define CCS_LIM_BINNING_SUB_TYPE_MONO_MAX_N 63U
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#define CCS_R_DATA_TRANSFER_IF_CAPABILITY CCI_REG8(0x1800)
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#define CCS_DATA_TRANSFER_IF_CAPABILITY_SUPPORTED BIT(0)
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#define CCS_DATA_TRANSFER_IF_CAPABILITY_POLLING BIT(2)
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#define CCS_R_SHADING_CORRECTION_CAPABILITY CCI_REG8(0x1900)
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#define CCS_SHADING_CORRECTION_CAPABILITY_COLOR_SHADING BIT(0)
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#define CCS_SHADING_CORRECTION_CAPABILITY_LUMINANCE_CORRECTION BIT(1)
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#define CCS_R_GREEN_IMBALANCE_CAPABILITY CCI_REG8(0x1901)
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#define CCS_GREEN_IMBALANCE_CAPABILITY_SUPPORTED BIT(0)
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#define CCS_R_MODULE_SPECIFIC_CORRECTION_CAPABILITY CCI_REG8(0x1903)
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#define CCS_R_DEFECT_CORRECTION_CAPABILITY CCI_REG16(0x1904)
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#define CCS_DEFECT_CORRECTION_CAPABILITY_MAPPED_DEFECT BIT(0)
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#define CCS_DEFECT_CORRECTION_CAPABILITY_DYNAMIC_COUPLET BIT(2)
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#define CCS_DEFECT_CORRECTION_CAPABILITY_DYNAMIC_SINGLE BIT(5)
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#define CCS_DEFECT_CORRECTION_CAPABILITY_COMBINED_DYNAMIC BIT(8)
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#define CCS_R_DEFECT_CORRECTION_CAPABILITY_2 CCI_REG16(0x1906)
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#define CCS_DEFECT_CORRECTION_CAPABILITY_2_DYNAMIC_TRIPLET BIT(3)
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#define CCS_R_NF_CAPABILITY CCI_REG8(0x1908)
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#define CCS_NF_CAPABILITY_LUMA BIT(0)
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#define CCS_NF_CAPABILITY_CHROMA BIT(1)
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#define CCS_NF_CAPABILITY_COMBINED BIT(2)
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#define CCS_R_OB_READOUT_CAPABILITY CCI_REG8(0x1980)
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#define CCS_OB_READOUT_CAPABILITY_CONTROLLABLE_READOUT BIT(0)
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#define CCS_OB_READOUT_CAPABILITY_VISIBLE_PIXEL_READOUT BIT(1)
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#define CCS_OB_READOUT_CAPABILITY_DIFFERENT_VC_READOUT BIT(2)
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#define CCS_OB_READOUT_CAPABILITY_DIFFERENT_DT_READOUT BIT(3)
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#define CCS_OB_READOUT_CAPABILITY_PROG_DATA_FORMAT BIT(4)
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#define CCS_R_COLOR_FEEDBACK_CAPABILITY CCI_REG8(0x1987)
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#define CCS_COLOR_FEEDBACK_CAPABILITY_KELVIN BIT(0)
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#define CCS_COLOR_FEEDBACK_CAPABILITY_AWB_GAIN BIT(1)
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#define CCS_R_CFA_PATTERN_CAPABILITY CCI_REG8(0x1990)
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#define CCS_CFA_PATTERN_CAPABILITY_BAYER 0U
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#define CCS_CFA_PATTERN_CAPABILITY_MONOCHROME 1U
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#define CCS_CFA_PATTERN_CAPABILITY_4X4_QUAD_BAYER 2U
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#define CCS_CFA_PATTERN_CAPABILITY_VENDOR_SPECIFIC 3U
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#define CCS_R_CFA_PATTERN_CONVERSION_CAPABILITY CCI_REG8(0x1991)
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#define CCS_CFA_PATTERN_CONVERSION_CAPABILITY_BAYER BIT(0)
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#define CCS_R_FLASH_MODE_CAPABILITY CCI_REG8(0x1a02)
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#define CCS_FLASH_MODE_CAPABILITY_SINGLE_STROBE BIT(0)
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#define CCS_R_SA_STROBE_MODE_CAPABILITY CCI_REG8(0x1a03)
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#define CCS_SA_STROBE_MODE_CAPABILITY_FIXED_WIDTH BIT(0)
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#define CCS_SA_STROBE_MODE_CAPABILITY_EDGE_CTRL BIT(1)
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#define CCS_R_RESET_MAX_DELAY CCI_REG8(0x1a10)
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#define CCS_R_RESET_MIN_TIME CCI_REG8(0x1a11)
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#define CCS_R_PDAF_CAPABILITY_1 CCI_REG8(0x1b80)
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#define CCS_PDAF_CAPABILITY_1_SUPPORTED BIT(0)
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#define CCS_PDAF_CAPABILITY_1_PROCESSED_BOTTOM_EMBEDDED BIT(1)
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#define CCS_PDAF_CAPABILITY_1_PROCESSED_INTERLEAVED BIT(2)
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#define CCS_PDAF_CAPABILITY_1_RAW_BOTTOM_EMBEDDED BIT(3)
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#define CCS_PDAF_CAPABILITY_1_RAW_INTERLEAVED BIT(4)
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#define CCS_PDAF_CAPABILITY_1_VISIBLE_PDAF_CORRECTION BIT(5)
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#define CCS_PDAF_CAPABILITY_1_VC_INTERLEAVING BIT(6)
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#define CCS_PDAF_CAPABILITY_1_DT_INTERLEAVING BIT(7)
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#define CCS_R_PDAF_CAPABILITY_2 CCI_REG8(0x1b81)
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#define CCS_PDAF_CAPABILITY_2_ROI BIT(0)
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#define CCS_PDAF_CAPABILITY_2_AFTER_DIGITAL_CROP BIT(1)
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#define CCS_PDAF_CAPABILITY_2_CTRL_RETIMED BIT(2)
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#define CCS_R_BRACKETING_LUT_CAPABILITY_1 CCI_REG8(0x1c00)
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#define CCS_BRACKETING_LUT_CAPABILITY_1_COARSE_INTEGRATION BIT(0)
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#define CCS_BRACKETING_LUT_CAPABILITY_1_GLOBAL_ANALOG_GAIN BIT(1)
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#define CCS_BRACKETING_LUT_CAPABILITY_1_FLASH BIT(4)
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#define CCS_BRACKETING_LUT_CAPABILITY_1_GLOBAL_DIGITAL_GAIN BIT(5)
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#define CCS_BRACKETING_LUT_CAPABILITY_1_ALTERNATE_GLOBAL_ANALOG_GAIN BIT(6)
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#define CCS_R_BRACKETING_LUT_CAPABILITY_2 CCI_REG8(0x1c01)
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#define CCS_BRACKETING_LUT_CAPABILITY_2_SINGLE_BRACKETING_MODE BIT(0)
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#define CCS_BRACKETING_LUT_CAPABILITY_2_LOOPED_BRACKETING_MODE BIT(1)
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#define CCS_R_BRACKETING_LUT_SIZE CCI_REG8(0x1c02)
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#endif /* __CCS_REGS_H__ */
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