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3704432fb1
Introduce an enum to specify whether the attribute is separate or shared. Factor out the bitmap handling for loop into a separate function. Tidy up error handling and add a NULL assignment to squish a false positive warning from GCC. Change ext_info shared type from boolean to enum and update in all drivers. Signed-off-by: Jonathan Cameron <jic23@kernel.org> Reviewed-by: Lars-Peter Clausen <lars@metafoo.de>
641 lines
16 KiB
C
641 lines
16 KiB
C
/*
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* AD5755, AD5755-1, AD5757, AD5735, AD5737 Digital to analog converters driver
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*
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* Copyright 2012 Analog Devices Inc.
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*
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* Licensed under the GPL-2.
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*/
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#include <linux/device.h>
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#include <linux/err.h>
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/spi/spi.h>
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#include <linux/slab.h>
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#include <linux/sysfs.h>
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#include <linux/delay.h>
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#include <linux/iio/iio.h>
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#include <linux/iio/sysfs.h>
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#include <linux/platform_data/ad5755.h>
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#define AD5755_NUM_CHANNELS 4
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#define AD5755_ADDR(x) ((x) << 16)
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#define AD5755_WRITE_REG_DATA(chan) (chan)
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#define AD5755_WRITE_REG_GAIN(chan) (0x08 | (chan))
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#define AD5755_WRITE_REG_OFFSET(chan) (0x10 | (chan))
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#define AD5755_WRITE_REG_CTRL(chan) (0x1c | (chan))
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#define AD5755_READ_REG_DATA(chan) (chan)
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#define AD5755_READ_REG_CTRL(chan) (0x4 | (chan))
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#define AD5755_READ_REG_GAIN(chan) (0x8 | (chan))
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#define AD5755_READ_REG_OFFSET(chan) (0xc | (chan))
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#define AD5755_READ_REG_CLEAR(chan) (0x10 | (chan))
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#define AD5755_READ_REG_SLEW(chan) (0x14 | (chan))
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#define AD5755_READ_REG_STATUS 0x18
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#define AD5755_READ_REG_MAIN 0x19
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#define AD5755_READ_REG_DC_DC 0x1a
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#define AD5755_CTRL_REG_SLEW 0x0
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#define AD5755_CTRL_REG_MAIN 0x1
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#define AD5755_CTRL_REG_DAC 0x2
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#define AD5755_CTRL_REG_DC_DC 0x3
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#define AD5755_CTRL_REG_SW 0x4
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#define AD5755_READ_FLAG 0x800000
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#define AD5755_NOOP 0x1CE000
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#define AD5755_DAC_INT_EN BIT(8)
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#define AD5755_DAC_CLR_EN BIT(7)
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#define AD5755_DAC_OUT_EN BIT(6)
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#define AD5755_DAC_INT_CURRENT_SENSE_RESISTOR BIT(5)
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#define AD5755_DAC_DC_DC_EN BIT(4)
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#define AD5755_DAC_VOLTAGE_OVERRANGE_EN BIT(3)
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#define AD5755_DC_DC_MAXV 0
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#define AD5755_DC_DC_FREQ_SHIFT 2
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#define AD5755_DC_DC_PHASE_SHIFT 4
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#define AD5755_EXT_DC_DC_COMP_RES BIT(6)
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#define AD5755_SLEW_STEP_SIZE_SHIFT 0
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#define AD5755_SLEW_RATE_SHIFT 3
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#define AD5755_SLEW_ENABLE BIT(12)
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/**
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* struct ad5755_chip_info - chip specific information
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* @channel_template: channel specification
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* @calib_shift: shift for the calibration data registers
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* @has_voltage_out: whether the chip has voltage outputs
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*/
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struct ad5755_chip_info {
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const struct iio_chan_spec channel_template;
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unsigned int calib_shift;
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bool has_voltage_out;
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};
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/**
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* struct ad5755_state - driver instance specific data
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* @spi: spi device the driver is attached to
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* @chip_info: chip model specific constants, available modes etc
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* @pwr_down: bitmask which contains hether a channel is powered down or not
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* @ctrl: software shadow of the channel ctrl registers
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* @channels: iio channel spec for the device
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* @data: spi transfer buffers
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*/
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struct ad5755_state {
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struct spi_device *spi;
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const struct ad5755_chip_info *chip_info;
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unsigned int pwr_down;
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unsigned int ctrl[AD5755_NUM_CHANNELS];
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struct iio_chan_spec channels[AD5755_NUM_CHANNELS];
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/*
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* DMA (thus cache coherency maintenance) requires the
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* transfer buffers to live in their own cache lines.
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*/
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union {
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u32 d32;
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u8 d8[4];
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} data[2] ____cacheline_aligned;
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};
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enum ad5755_type {
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ID_AD5755,
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ID_AD5757,
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ID_AD5735,
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ID_AD5737,
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};
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static int ad5755_write_unlocked(struct iio_dev *indio_dev,
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unsigned int reg, unsigned int val)
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{
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struct ad5755_state *st = iio_priv(indio_dev);
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st->data[0].d32 = cpu_to_be32((reg << 16) | val);
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return spi_write(st->spi, &st->data[0].d8[1], 3);
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}
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static int ad5755_write_ctrl_unlocked(struct iio_dev *indio_dev,
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unsigned int channel, unsigned int reg, unsigned int val)
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{
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return ad5755_write_unlocked(indio_dev,
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AD5755_WRITE_REG_CTRL(channel), (reg << 13) | val);
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}
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static int ad5755_write(struct iio_dev *indio_dev, unsigned int reg,
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unsigned int val)
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{
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int ret;
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mutex_lock(&indio_dev->mlock);
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ret = ad5755_write_unlocked(indio_dev, reg, val);
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mutex_unlock(&indio_dev->mlock);
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return ret;
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}
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static int ad5755_write_ctrl(struct iio_dev *indio_dev, unsigned int channel,
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unsigned int reg, unsigned int val)
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{
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int ret;
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mutex_lock(&indio_dev->mlock);
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ret = ad5755_write_ctrl_unlocked(indio_dev, channel, reg, val);
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mutex_unlock(&indio_dev->mlock);
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return ret;
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}
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static int ad5755_read(struct iio_dev *indio_dev, unsigned int addr)
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{
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struct ad5755_state *st = iio_priv(indio_dev);
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int ret;
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struct spi_transfer t[] = {
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{
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.tx_buf = &st->data[0].d8[1],
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.len = 3,
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.cs_change = 1,
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}, {
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.tx_buf = &st->data[1].d8[1],
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.rx_buf = &st->data[1].d8[1],
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.len = 3,
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},
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};
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mutex_lock(&indio_dev->mlock);
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st->data[0].d32 = cpu_to_be32(AD5755_READ_FLAG | (addr << 16));
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st->data[1].d32 = cpu_to_be32(AD5755_NOOP);
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ret = spi_sync_transfer(st->spi, t, ARRAY_SIZE(t));
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if (ret >= 0)
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ret = be32_to_cpu(st->data[1].d32) & 0xffff;
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mutex_unlock(&indio_dev->mlock);
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return ret;
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}
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static int ad5755_update_dac_ctrl(struct iio_dev *indio_dev,
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unsigned int channel, unsigned int set, unsigned int clr)
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{
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struct ad5755_state *st = iio_priv(indio_dev);
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int ret;
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st->ctrl[channel] |= set;
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st->ctrl[channel] &= ~clr;
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ret = ad5755_write_ctrl_unlocked(indio_dev, channel,
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AD5755_CTRL_REG_DAC, st->ctrl[channel]);
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return ret;
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}
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static int ad5755_set_channel_pwr_down(struct iio_dev *indio_dev,
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unsigned int channel, bool pwr_down)
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{
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struct ad5755_state *st = iio_priv(indio_dev);
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unsigned int mask = BIT(channel);
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mutex_lock(&indio_dev->mlock);
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if ((bool)(st->pwr_down & mask) == pwr_down)
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goto out_unlock;
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if (!pwr_down) {
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st->pwr_down &= ~mask;
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ad5755_update_dac_ctrl(indio_dev, channel,
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AD5755_DAC_INT_EN | AD5755_DAC_DC_DC_EN, 0);
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udelay(200);
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ad5755_update_dac_ctrl(indio_dev, channel,
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AD5755_DAC_OUT_EN, 0);
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} else {
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st->pwr_down |= mask;
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ad5755_update_dac_ctrl(indio_dev, channel,
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0, AD5755_DAC_INT_EN | AD5755_DAC_OUT_EN |
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AD5755_DAC_DC_DC_EN);
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}
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out_unlock:
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mutex_unlock(&indio_dev->mlock);
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return 0;
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}
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static const int ad5755_min_max_table[][2] = {
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[AD5755_MODE_VOLTAGE_0V_5V] = { 0, 5000 },
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[AD5755_MODE_VOLTAGE_0V_10V] = { 0, 10000 },
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[AD5755_MODE_VOLTAGE_PLUSMINUS_5V] = { -5000, 5000 },
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[AD5755_MODE_VOLTAGE_PLUSMINUS_10V] = { -10000, 10000 },
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[AD5755_MODE_CURRENT_4mA_20mA] = { 4, 20 },
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[AD5755_MODE_CURRENT_0mA_20mA] = { 0, 20 },
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[AD5755_MODE_CURRENT_0mA_24mA] = { 0, 24 },
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};
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static void ad5755_get_min_max(struct ad5755_state *st,
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struct iio_chan_spec const *chan, int *min, int *max)
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{
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enum ad5755_mode mode = st->ctrl[chan->channel] & 7;
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*min = ad5755_min_max_table[mode][0];
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*max = ad5755_min_max_table[mode][1];
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}
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static inline int ad5755_get_offset(struct ad5755_state *st,
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struct iio_chan_spec const *chan)
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{
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int min, max;
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ad5755_get_min_max(st, chan, &min, &max);
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return (min * (1 << chan->scan_type.realbits)) / (max - min);
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}
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static inline int ad5755_get_scale(struct ad5755_state *st,
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struct iio_chan_spec const *chan)
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{
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int min, max;
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ad5755_get_min_max(st, chan, &min, &max);
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return ((max - min) * 1000000000ULL) >> chan->scan_type.realbits;
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}
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static int ad5755_chan_reg_info(struct ad5755_state *st,
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struct iio_chan_spec const *chan, long info, bool write,
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unsigned int *reg, unsigned int *shift, unsigned int *offset)
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{
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switch (info) {
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case IIO_CHAN_INFO_RAW:
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if (write)
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*reg = AD5755_WRITE_REG_DATA(chan->address);
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else
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*reg = AD5755_READ_REG_DATA(chan->address);
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*shift = chan->scan_type.shift;
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*offset = 0;
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break;
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case IIO_CHAN_INFO_CALIBBIAS:
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if (write)
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*reg = AD5755_WRITE_REG_OFFSET(chan->address);
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else
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*reg = AD5755_READ_REG_OFFSET(chan->address);
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*shift = st->chip_info->calib_shift;
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*offset = 32768;
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break;
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case IIO_CHAN_INFO_CALIBSCALE:
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if (write)
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*reg = AD5755_WRITE_REG_GAIN(chan->address);
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else
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*reg = AD5755_READ_REG_GAIN(chan->address);
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*shift = st->chip_info->calib_shift;
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*offset = 0;
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static int ad5755_read_raw(struct iio_dev *indio_dev,
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const struct iio_chan_spec *chan, int *val, int *val2, long info)
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{
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struct ad5755_state *st = iio_priv(indio_dev);
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unsigned int reg, shift, offset;
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int ret;
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switch (info) {
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case IIO_CHAN_INFO_SCALE:
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*val = 0;
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*val2 = ad5755_get_scale(st, chan);
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return IIO_VAL_INT_PLUS_NANO;
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case IIO_CHAN_INFO_OFFSET:
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*val = ad5755_get_offset(st, chan);
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return IIO_VAL_INT;
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default:
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ret = ad5755_chan_reg_info(st, chan, info, false,
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®, &shift, &offset);
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if (ret)
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return ret;
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ret = ad5755_read(indio_dev, reg);
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if (ret < 0)
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return ret;
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*val = (ret - offset) >> shift;
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return IIO_VAL_INT;
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}
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return -EINVAL;
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}
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static int ad5755_write_raw(struct iio_dev *indio_dev,
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const struct iio_chan_spec *chan, int val, int val2, long info)
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{
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struct ad5755_state *st = iio_priv(indio_dev);
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unsigned int shift, reg, offset;
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int ret;
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ret = ad5755_chan_reg_info(st, chan, info, true,
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®, &shift, &offset);
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if (ret)
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return ret;
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val <<= shift;
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val += offset;
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if (val < 0 || val > 0xffff)
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return -EINVAL;
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return ad5755_write(indio_dev, reg, val);
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}
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static ssize_t ad5755_read_powerdown(struct iio_dev *indio_dev, uintptr_t priv,
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const struct iio_chan_spec *chan, char *buf)
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{
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struct ad5755_state *st = iio_priv(indio_dev);
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return sprintf(buf, "%d\n",
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(bool)(st->pwr_down & (1 << chan->channel)));
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}
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static ssize_t ad5755_write_powerdown(struct iio_dev *indio_dev, uintptr_t priv,
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struct iio_chan_spec const *chan, const char *buf, size_t len)
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{
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bool pwr_down;
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int ret;
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ret = strtobool(buf, &pwr_down);
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if (ret)
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return ret;
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ret = ad5755_set_channel_pwr_down(indio_dev, chan->channel, pwr_down);
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return ret ? ret : len;
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}
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static const struct iio_info ad5755_info = {
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.read_raw = ad5755_read_raw,
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.write_raw = ad5755_write_raw,
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.driver_module = THIS_MODULE,
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};
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static const struct iio_chan_spec_ext_info ad5755_ext_info[] = {
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{
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.name = "powerdown",
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.read = ad5755_read_powerdown,
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.write = ad5755_write_powerdown,
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.shared = IIO_SEPARATE,
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},
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{ },
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};
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#define AD5755_CHANNEL(_bits) { \
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.indexed = 1, \
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.output = 1, \
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.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
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BIT(IIO_CHAN_INFO_SCALE) | \
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BIT(IIO_CHAN_INFO_OFFSET) | \
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BIT(IIO_CHAN_INFO_CALIBSCALE) | \
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BIT(IIO_CHAN_INFO_CALIBBIAS), \
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.scan_type = IIO_ST('u', (_bits), 16, 16 - (_bits)), \
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.ext_info = ad5755_ext_info, \
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}
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static const struct ad5755_chip_info ad5755_chip_info_tbl[] = {
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[ID_AD5735] = {
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.channel_template = AD5755_CHANNEL(14),
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.has_voltage_out = true,
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.calib_shift = 4,
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},
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[ID_AD5737] = {
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.channel_template = AD5755_CHANNEL(14),
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.has_voltage_out = false,
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.calib_shift = 4,
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},
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[ID_AD5755] = {
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.channel_template = AD5755_CHANNEL(16),
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.has_voltage_out = true,
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.calib_shift = 0,
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},
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[ID_AD5757] = {
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.channel_template = AD5755_CHANNEL(16),
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.has_voltage_out = false,
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.calib_shift = 0,
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},
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};
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static bool ad5755_is_valid_mode(struct ad5755_state *st, enum ad5755_mode mode)
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{
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switch (mode) {
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case AD5755_MODE_VOLTAGE_0V_5V:
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case AD5755_MODE_VOLTAGE_0V_10V:
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case AD5755_MODE_VOLTAGE_PLUSMINUS_5V:
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case AD5755_MODE_VOLTAGE_PLUSMINUS_10V:
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return st->chip_info->has_voltage_out;
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case AD5755_MODE_CURRENT_4mA_20mA:
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case AD5755_MODE_CURRENT_0mA_20mA:
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case AD5755_MODE_CURRENT_0mA_24mA:
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return true;
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default:
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return false;
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}
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}
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static int ad5755_setup_pdata(struct iio_dev *indio_dev,
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const struct ad5755_platform_data *pdata)
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{
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struct ad5755_state *st = iio_priv(indio_dev);
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unsigned int val;
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unsigned int i;
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int ret;
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if (pdata->dc_dc_phase > AD5755_DC_DC_PHASE_90_DEGREE ||
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pdata->dc_dc_freq > AD5755_DC_DC_FREQ_650kHZ ||
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pdata->dc_dc_maxv > AD5755_DC_DC_MAXV_29V5)
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return -EINVAL;
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val = pdata->dc_dc_maxv << AD5755_DC_DC_MAXV;
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val |= pdata->dc_dc_freq << AD5755_DC_DC_FREQ_SHIFT;
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val |= pdata->dc_dc_phase << AD5755_DC_DC_PHASE_SHIFT;
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if (pdata->ext_dc_dc_compenstation_resistor)
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val |= AD5755_EXT_DC_DC_COMP_RES;
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ret = ad5755_write_ctrl(indio_dev, 0, AD5755_CTRL_REG_DC_DC, val);
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if (ret < 0)
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return ret;
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for (i = 0; i < ARRAY_SIZE(pdata->dac); ++i) {
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val = pdata->dac[i].slew.step_size <<
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AD5755_SLEW_STEP_SIZE_SHIFT;
|
|
val |= pdata->dac[i].slew.rate <<
|
|
AD5755_SLEW_RATE_SHIFT;
|
|
if (pdata->dac[i].slew.enable)
|
|
val |= AD5755_SLEW_ENABLE;
|
|
|
|
ret = ad5755_write_ctrl(indio_dev, i,
|
|
AD5755_CTRL_REG_SLEW, val);
|
|
if (ret < 0)
|
|
return ret;
|
|
}
|
|
|
|
for (i = 0; i < ARRAY_SIZE(pdata->dac); ++i) {
|
|
if (!ad5755_is_valid_mode(st, pdata->dac[i].mode))
|
|
return -EINVAL;
|
|
|
|
val = 0;
|
|
if (!pdata->dac[i].ext_current_sense_resistor)
|
|
val |= AD5755_DAC_INT_CURRENT_SENSE_RESISTOR;
|
|
if (pdata->dac[i].enable_voltage_overrange)
|
|
val |= AD5755_DAC_VOLTAGE_OVERRANGE_EN;
|
|
val |= pdata->dac[i].mode;
|
|
|
|
ret = ad5755_update_dac_ctrl(indio_dev, i, val, 0);
|
|
if (ret < 0)
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static bool ad5755_is_voltage_mode(enum ad5755_mode mode)
|
|
{
|
|
switch (mode) {
|
|
case AD5755_MODE_VOLTAGE_0V_5V:
|
|
case AD5755_MODE_VOLTAGE_0V_10V:
|
|
case AD5755_MODE_VOLTAGE_PLUSMINUS_5V:
|
|
case AD5755_MODE_VOLTAGE_PLUSMINUS_10V:
|
|
return true;
|
|
default:
|
|
return false;
|
|
}
|
|
}
|
|
|
|
static int ad5755_init_channels(struct iio_dev *indio_dev,
|
|
const struct ad5755_platform_data *pdata)
|
|
{
|
|
struct ad5755_state *st = iio_priv(indio_dev);
|
|
struct iio_chan_spec *channels = st->channels;
|
|
unsigned int i;
|
|
|
|
for (i = 0; i < AD5755_NUM_CHANNELS; ++i) {
|
|
channels[i] = st->chip_info->channel_template;
|
|
channels[i].channel = i;
|
|
channels[i].address = i;
|
|
if (pdata && ad5755_is_voltage_mode(pdata->dac[i].mode))
|
|
channels[i].type = IIO_VOLTAGE;
|
|
else
|
|
channels[i].type = IIO_CURRENT;
|
|
}
|
|
|
|
indio_dev->channels = channels;
|
|
|
|
return 0;
|
|
}
|
|
|
|
#define AD5755_DEFAULT_DAC_PDATA { \
|
|
.mode = AD5755_MODE_CURRENT_4mA_20mA, \
|
|
.ext_current_sense_resistor = true, \
|
|
.enable_voltage_overrange = false, \
|
|
.slew = { \
|
|
.enable = false, \
|
|
.rate = AD5755_SLEW_RATE_64k, \
|
|
.step_size = AD5755_SLEW_STEP_SIZE_1, \
|
|
}, \
|
|
}
|
|
|
|
static const struct ad5755_platform_data ad5755_default_pdata = {
|
|
.ext_dc_dc_compenstation_resistor = false,
|
|
.dc_dc_phase = AD5755_DC_DC_PHASE_ALL_SAME_EDGE,
|
|
.dc_dc_freq = AD5755_DC_DC_FREQ_410kHZ,
|
|
.dc_dc_maxv = AD5755_DC_DC_MAXV_23V,
|
|
.dac = {
|
|
[0] = AD5755_DEFAULT_DAC_PDATA,
|
|
[1] = AD5755_DEFAULT_DAC_PDATA,
|
|
[2] = AD5755_DEFAULT_DAC_PDATA,
|
|
[3] = AD5755_DEFAULT_DAC_PDATA,
|
|
},
|
|
};
|
|
|
|
static int ad5755_probe(struct spi_device *spi)
|
|
{
|
|
enum ad5755_type type = spi_get_device_id(spi)->driver_data;
|
|
const struct ad5755_platform_data *pdata = dev_get_platdata(&spi->dev);
|
|
struct iio_dev *indio_dev;
|
|
struct ad5755_state *st;
|
|
int ret;
|
|
|
|
indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
|
|
if (indio_dev == NULL) {
|
|
dev_err(&spi->dev, "Failed to allocate iio device\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
st = iio_priv(indio_dev);
|
|
spi_set_drvdata(spi, indio_dev);
|
|
|
|
st->chip_info = &ad5755_chip_info_tbl[type];
|
|
st->spi = spi;
|
|
st->pwr_down = 0xf;
|
|
|
|
indio_dev->dev.parent = &spi->dev;
|
|
indio_dev->name = spi_get_device_id(spi)->name;
|
|
indio_dev->info = &ad5755_info;
|
|
indio_dev->modes = INDIO_DIRECT_MODE;
|
|
indio_dev->num_channels = AD5755_NUM_CHANNELS;
|
|
|
|
if (!pdata)
|
|
pdata = &ad5755_default_pdata;
|
|
|
|
ret = ad5755_init_channels(indio_dev, pdata);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = ad5755_setup_pdata(indio_dev, pdata);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = iio_device_register(indio_dev);
|
|
if (ret) {
|
|
dev_err(&spi->dev, "Failed to register iio device: %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int ad5755_remove(struct spi_device *spi)
|
|
{
|
|
struct iio_dev *indio_dev = spi_get_drvdata(spi);
|
|
|
|
iio_device_unregister(indio_dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct spi_device_id ad5755_id[] = {
|
|
{ "ad5755", ID_AD5755 },
|
|
{ "ad5755-1", ID_AD5755 },
|
|
{ "ad5757", ID_AD5757 },
|
|
{ "ad5735", ID_AD5735 },
|
|
{ "ad5737", ID_AD5737 },
|
|
{}
|
|
};
|
|
MODULE_DEVICE_TABLE(spi, ad5755_id);
|
|
|
|
static struct spi_driver ad5755_driver = {
|
|
.driver = {
|
|
.name = "ad5755",
|
|
.owner = THIS_MODULE,
|
|
},
|
|
.probe = ad5755_probe,
|
|
.remove = ad5755_remove,
|
|
.id_table = ad5755_id,
|
|
};
|
|
module_spi_driver(ad5755_driver);
|
|
|
|
MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
|
|
MODULE_DESCRIPTION("Analog Devices AD5755/55-1/57/35/37 DAC");
|
|
MODULE_LICENSE("GPL v2");
|