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When using clock gatings to save power, there are some known issues: 1. core clock gating (DCLCGE) must be disabled during D0 and D3 entry and updating SRAM banks (VDRTCTL0). 2. DSP trunk clock gating (DTCGE) can cause FW crashes, disable it in D0. To align with the new W/A flow from FW team, we must set VDRTCTL0.D3PGD to 1 (D3 power gating disabled) at first startup and keep it all the time. ADSP will be in D0 on first boot by BIOS part of WA. Required delays must be preserved (waiting for HW to stabilize, after enabling CCG, changing SRAM PG, D3PG). D3->D0: 1. Disable core clock gating (VDRTCTL2.DCLCGE = 0) 2. Enable other CG apart from DTCG and DCLCG (VDRTCTL2. DCLCGE and DTCGE = 0) 3. Disable D3PG (VDRTCTL0.D3PGD = 1) 4. Power up necessary SRAM and wait at least for 18 clock cycles for every bank you have powered up 5. Set D0 state(PMCS.PS = 0), wait for HW 6. Restore MCLK (clkctl.smos, disabled in D3 entry point 4) 7. Stall and reset core, set CSR 8. Enable core clock gating (VDRTCTL2.DCLCGE = 1), delay 50 us 9. Unreset core 10.Load FW, configure PLL and other necessary things 11.Unstall core Changing SRAM PG during D0: 1. Disable core clock gating (VDRTCTL2.DCLCGE = 0) 2. Set PG mask 3. Wait at least for 18 clock cycles for every bank you have powered up 4. Enable core clock gating, delay 50 us D0->D3: 1. Disable core clock gating (DCLCGE = 0) 2. Stall and reset core 3. Power down entire SRAM and wait at least for 18 clock cycles for every bank (Enable SRAM PG (ISRAMPGE = 0x3FF, DSRAMPGE = 0xFFFFF, D3SRAMPGD = 0), remember about preserving VDRTCTL0.D3PGD = 1) 4. Shutdown PLL, disable MCLK(clkctl.smos = 0), Enable DTCG to save power 5. Set D3 state(PMCS.PS = 3), delay 50 us 6. Enable core clock gating, delay 50 us Signed-off-by: Jie Yang <yang.jie@intel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
703 lines
19 KiB
C
703 lines
19 KiB
C
/*
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* Intel Haswell SST DSP driver
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*
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* Copyright (C) 2013, Intel Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License version
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* 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/delay.h>
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#include <linux/fs.h>
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#include <linux/slab.h>
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#include <linux/device.h>
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#include <linux/sched.h>
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#include <linux/export.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <linux/dma-mapping.h>
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#include <linux/platform_device.h>
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#include <linux/pci.h>
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#include <linux/firmware.h>
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#include <linux/pm_runtime.h>
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#include "sst-dsp.h"
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#include "sst-dsp-priv.h"
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#include "sst-haswell-ipc.h"
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#include <trace/events/hswadsp.h>
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#define SST_HSW_FW_SIGNATURE_SIZE 4
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#define SST_HSW_FW_SIGN "$SST"
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#define SST_HSW_FW_LIB_SIGN "$LIB"
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#define SST_WPT_SHIM_OFFSET 0xFB000
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#define SST_LP_SHIM_OFFSET 0xE7000
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#define SST_WPT_IRAM_OFFSET 0xA0000
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#define SST_LP_IRAM_OFFSET 0x80000
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#define SST_WPT_DSP_DRAM_OFFSET 0x400000
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#define SST_WPT_DSP_IRAM_OFFSET 0x00000
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#define SST_LPT_DSP_DRAM_OFFSET 0x400000
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#define SST_LPT_DSP_IRAM_OFFSET 0x00000
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#define SST_SHIM_PM_REG 0x84
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#define SST_HSW_IRAM 1
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#define SST_HSW_DRAM 2
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#define SST_HSW_REGS 3
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struct dma_block_info {
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__le32 type; /* IRAM/DRAM */
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__le32 size; /* Bytes */
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__le32 ram_offset; /* Offset in I/DRAM */
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__le32 rsvd; /* Reserved field */
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} __attribute__((packed));
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struct fw_module_info {
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__le32 persistent_size;
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__le32 scratch_size;
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} __attribute__((packed));
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struct fw_header {
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unsigned char signature[SST_HSW_FW_SIGNATURE_SIZE]; /* FW signature */
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__le32 file_size; /* size of fw minus this header */
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__le32 modules; /* # of modules */
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__le32 file_format; /* version of header format */
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__le32 reserved[4];
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} __attribute__((packed));
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struct fw_module_header {
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unsigned char signature[SST_HSW_FW_SIGNATURE_SIZE]; /* module signature */
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__le32 mod_size; /* size of module */
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__le32 blocks; /* # of blocks */
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__le16 padding;
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__le16 type; /* codec type, pp lib */
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__le32 entry_point;
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struct fw_module_info info;
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} __attribute__((packed));
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static void hsw_free(struct sst_dsp *sst);
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static int hsw_parse_module(struct sst_dsp *dsp, struct sst_fw *fw,
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struct fw_module_header *module)
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{
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struct dma_block_info *block;
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struct sst_module *mod;
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struct sst_module_template template;
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int count, ret;
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void __iomem *ram;
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/* TODO: allowed module types need to be configurable */
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if (module->type != SST_HSW_MODULE_BASE_FW
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&& module->type != SST_HSW_MODULE_PCM_SYSTEM
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&& module->type != SST_HSW_MODULE_PCM
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&& module->type != SST_HSW_MODULE_PCM_REFERENCE
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&& module->type != SST_HSW_MODULE_PCM_CAPTURE
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&& module->type != SST_HSW_MODULE_LPAL)
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return 0;
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dev_dbg(dsp->dev, "new module sign 0x%s size 0x%x blocks 0x%x type 0x%x\n",
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module->signature, module->mod_size,
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module->blocks, module->type);
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dev_dbg(dsp->dev, " entrypoint 0x%x\n", module->entry_point);
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dev_dbg(dsp->dev, " persistent 0x%x scratch 0x%x\n",
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module->info.persistent_size, module->info.scratch_size);
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memset(&template, 0, sizeof(template));
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template.id = module->type;
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template.entry = module->entry_point - 4;
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template.persistent_size = module->info.persistent_size;
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template.scratch_size = module->info.scratch_size;
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mod = sst_module_new(fw, &template, NULL);
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if (mod == NULL)
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return -ENOMEM;
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block = (void *)module + sizeof(*module);
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for (count = 0; count < module->blocks; count++) {
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if (block->size <= 0) {
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dev_err(dsp->dev,
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"error: block %d size invalid\n", count);
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sst_module_free(mod);
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return -EINVAL;
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}
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switch (block->type) {
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case SST_HSW_IRAM:
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ram = dsp->addr.lpe;
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mod->offset =
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block->ram_offset + dsp->addr.iram_offset;
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mod->type = SST_MEM_IRAM;
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break;
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case SST_HSW_DRAM:
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ram = dsp->addr.lpe;
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mod->offset = block->ram_offset;
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mod->type = SST_MEM_DRAM;
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break;
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default:
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dev_err(dsp->dev, "error: bad type 0x%x for block 0x%x\n",
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block->type, count);
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sst_module_free(mod);
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return -EINVAL;
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}
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mod->size = block->size;
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mod->data = (void *)block + sizeof(*block);
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mod->data_offset = mod->data - fw->dma_buf;
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dev_dbg(dsp->dev, "module block %d type 0x%x "
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"size 0x%x ==> ram %p offset 0x%x\n",
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count, mod->type, block->size, ram,
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block->ram_offset);
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ret = sst_module_alloc_blocks(mod);
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if (ret < 0) {
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dev_err(dsp->dev, "error: could not allocate blocks for module %d\n",
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count);
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sst_module_free(mod);
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return ret;
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}
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block = (void *)block + sizeof(*block) + block->size;
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}
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return 0;
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}
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static int hsw_parse_fw_image(struct sst_fw *sst_fw)
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{
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struct fw_header *header;
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struct fw_module_header *module;
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struct sst_dsp *dsp = sst_fw->dsp;
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int ret, count;
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/* Read the header information from the data pointer */
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header = (struct fw_header *)sst_fw->dma_buf;
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/* verify FW */
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if ((strncmp(header->signature, SST_HSW_FW_SIGN, 4) != 0) ||
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(sst_fw->size != header->file_size + sizeof(*header))) {
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dev_err(dsp->dev, "error: invalid fw sign/filesize mismatch\n");
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return -EINVAL;
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}
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dev_dbg(dsp->dev, "header size=0x%x modules=0x%x fmt=0x%x size=%zu\n",
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header->file_size, header->modules,
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header->file_format, sizeof(*header));
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/* parse each module */
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module = (void *)sst_fw->dma_buf + sizeof(*header);
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for (count = 0; count < header->modules; count++) {
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/* module */
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ret = hsw_parse_module(dsp, sst_fw, module);
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if (ret < 0) {
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dev_err(dsp->dev, "error: invalid module %d\n", count);
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return ret;
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}
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module = (void *)module + sizeof(*module) + module->mod_size;
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}
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/* allocate scratch mem regions */
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sst_block_alloc_scratch(dsp);
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return 0;
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}
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static irqreturn_t hsw_irq(int irq, void *context)
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{
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struct sst_dsp *sst = (struct sst_dsp *) context;
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u32 isr;
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int ret = IRQ_NONE;
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spin_lock(&sst->spinlock);
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/* Interrupt arrived, check src */
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isr = sst_dsp_shim_read_unlocked(sst, SST_ISRX);
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if (isr & SST_ISRX_DONE) {
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trace_sst_irq_done(isr,
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sst_dsp_shim_read_unlocked(sst, SST_IMRX));
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/* Mask Done interrupt before return */
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sst_dsp_shim_update_bits_unlocked(sst, SST_IMRX,
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SST_IMRX_DONE, SST_IMRX_DONE);
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ret = IRQ_WAKE_THREAD;
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}
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if (isr & SST_ISRX_BUSY) {
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trace_sst_irq_busy(isr,
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sst_dsp_shim_read_unlocked(sst, SST_IMRX));
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/* Mask Busy interrupt before return */
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sst_dsp_shim_update_bits_unlocked(sst, SST_IMRX,
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SST_IMRX_BUSY, SST_IMRX_BUSY);
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ret = IRQ_WAKE_THREAD;
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}
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spin_unlock(&sst->spinlock);
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return ret;
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}
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static void hsw_set_dsp_D3(struct sst_dsp *sst)
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{
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u32 val;
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u32 reg;
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/* Disable core clock gating (VDRTCTL2.DCLCGE = 0) */
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reg = readl(sst->addr.pci_cfg + SST_VDRTCTL2);
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reg &= ~(SST_VDRTCL2_DCLCGE | SST_VDRTCL2_DTCGE);
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writel(reg, sst->addr.pci_cfg + SST_VDRTCTL2);
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/* enable power gating and switch off DRAM & IRAM blocks */
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val = readl(sst->addr.pci_cfg + SST_VDRTCTL0);
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val |= SST_VDRTCL0_DSRAMPGE_MASK |
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SST_VDRTCL0_ISRAMPGE_MASK;
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val &= ~(SST_VDRTCL0_D3PGD | SST_VDRTCL0_D3SRAMPGD);
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writel(val, sst->addr.pci_cfg + SST_VDRTCTL0);
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/* switch off audio PLL */
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val = readl(sst->addr.pci_cfg + SST_VDRTCTL2);
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val |= SST_VDRTCL2_APLLSE_MASK;
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writel(val, sst->addr.pci_cfg + SST_VDRTCTL2);
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/* disable MCLK(clkctl.smos = 0) */
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sst_dsp_shim_update_bits_unlocked(sst, SST_CLKCTL,
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SST_CLKCTL_MASK, 0);
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/* Set D3 state, delay 50 us */
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val = readl(sst->addr.pci_cfg + SST_PMCS);
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val |= SST_PMCS_PS_MASK;
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writel(val, sst->addr.pci_cfg + SST_PMCS);
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udelay(50);
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/* Enable core clock gating (VDRTCTL2.DCLCGE = 1), delay 50 us */
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reg = readl(sst->addr.pci_cfg + SST_VDRTCTL2);
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reg |= SST_VDRTCL2_DCLCGE | SST_VDRTCL2_DTCGE;
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writel(reg, sst->addr.pci_cfg + SST_VDRTCTL2);
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udelay(50);
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}
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static void hsw_reset(struct sst_dsp *sst)
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{
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/* put DSP into reset and stall */
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sst_dsp_shim_update_bits_unlocked(sst, SST_CSR,
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SST_CSR_RST | SST_CSR_STALL,
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SST_CSR_RST | SST_CSR_STALL);
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/* keep in reset for 10ms */
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mdelay(10);
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/* take DSP out of reset and keep stalled for FW loading */
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sst_dsp_shim_update_bits_unlocked(sst, SST_CSR,
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SST_CSR_RST | SST_CSR_STALL, SST_CSR_STALL);
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}
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static int hsw_set_dsp_D0(struct sst_dsp *sst)
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{
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int tries = 10;
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u32 reg;
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/* Disable core clock gating (VDRTCTL2.DCLCGE = 0) */
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reg = readl(sst->addr.pci_cfg + SST_VDRTCTL2);
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reg &= ~(SST_VDRTCL2_DCLCGE | SST_VDRTCL2_DTCGE);
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writel(reg, sst->addr.pci_cfg + SST_VDRTCTL2);
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/* Disable D3PG (VDRTCTL0.D3PGD = 1) */
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reg = readl(sst->addr.pci_cfg + SST_VDRTCTL0);
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reg |= SST_VDRTCL0_D3PGD;
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writel(reg, sst->addr.pci_cfg + SST_VDRTCTL0);
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/* Set D0 state */
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reg = readl(sst->addr.pci_cfg + SST_PMCS);
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reg &= ~SST_PMCS_PS_MASK;
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writel(reg, sst->addr.pci_cfg + SST_PMCS);
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/* check that ADSP shim is enabled */
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while (tries--) {
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reg = readl(sst->addr.pci_cfg + SST_PMCS) & SST_PMCS_PS_MASK;
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if (reg == 0)
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goto finish;
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msleep(1);
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}
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return -ENODEV;
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finish:
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/* select SSP1 19.2MHz base clock, SSP clock 0, turn off Low Power Clock */
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sst_dsp_shim_update_bits_unlocked(sst, SST_CSR,
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SST_CSR_S1IOCS | SST_CSR_SBCS1 | SST_CSR_LPCS, 0x0);
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/* stall DSP core, set clk to 192/96Mhz */
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sst_dsp_shim_update_bits_unlocked(sst,
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SST_CSR, SST_CSR_STALL | SST_CSR_DCS_MASK,
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SST_CSR_STALL | SST_CSR_DCS(4));
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/* Set 24MHz MCLK, prevent local clock gating, enable SSP0 clock */
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sst_dsp_shim_update_bits_unlocked(sst, SST_CLKCTL,
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SST_CLKCTL_MASK | SST_CLKCTL_DCPLCG | SST_CLKCTL_SCOE0,
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SST_CLKCTL_MASK | SST_CLKCTL_DCPLCG | SST_CLKCTL_SCOE0);
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/* Stall and reset core, set CSR */
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hsw_reset(sst);
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/* Enable core clock gating (VDRTCTL2.DCLCGE = 1), delay 50 us */
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reg = readl(sst->addr.pci_cfg + SST_VDRTCTL2);
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reg |= SST_VDRTCL2_DCLCGE | SST_VDRTCL2_DTCGE;
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writel(reg, sst->addr.pci_cfg + SST_VDRTCTL2);
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udelay(50);
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/* switch on audio PLL */
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reg = readl(sst->addr.pci_cfg + SST_VDRTCTL2);
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reg &= ~SST_VDRTCL2_APLLSE_MASK;
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writel(reg, sst->addr.pci_cfg + SST_VDRTCTL2);
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/* set default power gating control, enable power gating control for all blocks. that is,
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can't be accessed, please enable each block before accessing. */
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reg = readl(sst->addr.pci_cfg + SST_VDRTCTL0);
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reg |= SST_VDRTCL0_DSRAMPGE_MASK | SST_VDRTCL0_ISRAMPGE_MASK;
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writel(reg, sst->addr.pci_cfg + SST_VDRTCTL0);
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/* disable DMA finish function for SSP0 & SSP1 */
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sst_dsp_shim_update_bits_unlocked(sst, SST_CSR2, SST_CSR2_SDFD_SSP1,
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SST_CSR2_SDFD_SSP1);
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/* set on-demond mode on engine 0,1 for all channels */
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sst_dsp_shim_update_bits(sst, SST_HMDC,
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SST_HMDC_HDDA_E0_ALLCH | SST_HMDC_HDDA_E1_ALLCH,
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SST_HMDC_HDDA_E0_ALLCH | SST_HMDC_HDDA_E1_ALLCH);
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/* Enable Interrupt from both sides */
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sst_dsp_shim_update_bits(sst, SST_IMRX, (SST_IMRX_BUSY | SST_IMRX_DONE),
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0x0);
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sst_dsp_shim_update_bits(sst, SST_IMRD, (SST_IMRD_DONE | SST_IMRD_BUSY |
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SST_IMRD_SSP0 | SST_IMRD_DMAC), 0x0);
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/* clear IPC registers */
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sst_dsp_shim_write(sst, SST_IPCX, 0x0);
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sst_dsp_shim_write(sst, SST_IPCD, 0x0);
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sst_dsp_shim_write(sst, 0x80, 0x6);
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sst_dsp_shim_write(sst, 0xe0, 0x300a);
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return 0;
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}
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static void hsw_boot(struct sst_dsp *sst)
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{
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/* set oportunistic mode on engine 0,1 for all channels */
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sst_dsp_shim_update_bits(sst, SST_HMDC,
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SST_HMDC_HDDA_E0_ALLCH | SST_HMDC_HDDA_E1_ALLCH, 0);
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/* set DSP to RUN */
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sst_dsp_shim_update_bits_unlocked(sst, SST_CSR, SST_CSR_STALL, 0x0);
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}
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static void hsw_stall(struct sst_dsp *sst)
|
|
{
|
|
/* stall DSP */
|
|
sst_dsp_shim_update_bits(sst, SST_CSR,
|
|
SST_CSR_24MHZ_LPCS | SST_CSR_STALL,
|
|
SST_CSR_STALL | SST_CSR_24MHZ_LPCS);
|
|
}
|
|
|
|
static void hsw_sleep(struct sst_dsp *sst)
|
|
{
|
|
dev_dbg(sst->dev, "HSW_PM dsp runtime suspend\n");
|
|
|
|
/* put DSP into reset and stall */
|
|
sst_dsp_shim_update_bits(sst, SST_CSR,
|
|
SST_CSR_24MHZ_LPCS | SST_CSR_RST | SST_CSR_STALL,
|
|
SST_CSR_RST | SST_CSR_STALL | SST_CSR_24MHZ_LPCS);
|
|
|
|
hsw_set_dsp_D3(sst);
|
|
dev_dbg(sst->dev, "HSW_PM dsp runtime suspend exit\n");
|
|
}
|
|
|
|
static int hsw_wake(struct sst_dsp *sst)
|
|
{
|
|
int ret;
|
|
|
|
dev_dbg(sst->dev, "HSW_PM dsp runtime resume\n");
|
|
|
|
ret = hsw_set_dsp_D0(sst);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
dev_dbg(sst->dev, "HSW_PM dsp runtime resume exit\n");
|
|
|
|
return 0;
|
|
}
|
|
|
|
struct sst_adsp_memregion {
|
|
u32 start;
|
|
u32 end;
|
|
int blocks;
|
|
enum sst_mem_type type;
|
|
};
|
|
|
|
/* lynx point ADSP mem regions */
|
|
static const struct sst_adsp_memregion lp_region[] = {
|
|
{0x00000, 0x40000, 8, SST_MEM_DRAM}, /* D-SRAM0 - 8 * 32kB */
|
|
{0x40000, 0x80000, 8, SST_MEM_DRAM}, /* D-SRAM1 - 8 * 32kB */
|
|
{0x80000, 0xE0000, 12, SST_MEM_IRAM}, /* I-SRAM - 12 * 32kB */
|
|
};
|
|
|
|
/* wild cat point ADSP mem regions */
|
|
static const struct sst_adsp_memregion wpt_region[] = {
|
|
{0x00000, 0xA0000, 20, SST_MEM_DRAM}, /* D-SRAM0,D-SRAM1,D-SRAM2 - 20 * 32kB */
|
|
{0xA0000, 0xF0000, 10, SST_MEM_IRAM}, /* I-SRAM - 10 * 32kB */
|
|
};
|
|
|
|
static int hsw_acpi_resource_map(struct sst_dsp *sst, struct sst_pdata *pdata)
|
|
{
|
|
/* ADSP DRAM & IRAM */
|
|
sst->addr.lpe_base = pdata->lpe_base;
|
|
sst->addr.lpe = ioremap(pdata->lpe_base, pdata->lpe_size);
|
|
if (!sst->addr.lpe)
|
|
return -ENODEV;
|
|
|
|
/* ADSP PCI MMIO config space */
|
|
sst->addr.pci_cfg = ioremap(pdata->pcicfg_base, pdata->pcicfg_size);
|
|
if (!sst->addr.pci_cfg) {
|
|
iounmap(sst->addr.lpe);
|
|
return -ENODEV;
|
|
}
|
|
|
|
/* SST Shim */
|
|
sst->addr.shim = sst->addr.lpe + sst->addr.shim_offset;
|
|
return 0;
|
|
}
|
|
|
|
struct sst_sram_shift {
|
|
u32 dev_id; /* SST Device IDs */
|
|
u32 iram_shift;
|
|
u32 dram_shift;
|
|
};
|
|
|
|
static const struct sst_sram_shift sram_shift[] = {
|
|
{SST_DEV_ID_LYNX_POINT, 6, 16}, /* lp */
|
|
{SST_DEV_ID_WILDCAT_POINT, 2, 12}, /* wpt */
|
|
};
|
|
static u32 hsw_block_get_bit(struct sst_mem_block *block)
|
|
{
|
|
u32 bit = 0, shift = 0, index;
|
|
struct sst_dsp *sst = block->dsp;
|
|
|
|
for (index = 0; index < ARRAY_SIZE(sram_shift); index++) {
|
|
if (sram_shift[index].dev_id == sst->id)
|
|
break;
|
|
}
|
|
|
|
if (index < ARRAY_SIZE(sram_shift)) {
|
|
switch (block->type) {
|
|
case SST_MEM_DRAM:
|
|
shift = sram_shift[index].dram_shift;
|
|
break;
|
|
case SST_MEM_IRAM:
|
|
shift = sram_shift[index].iram_shift;
|
|
break;
|
|
default:
|
|
shift = 0;
|
|
}
|
|
} else
|
|
shift = 0;
|
|
|
|
bit = 1 << (block->index + shift);
|
|
|
|
return bit;
|
|
}
|
|
|
|
/*dummy read a SRAM block.*/
|
|
static void sst_mem_block_dummy_read(struct sst_mem_block *block)
|
|
{
|
|
u32 size;
|
|
u8 tmp_buf[4];
|
|
struct sst_dsp *sst = block->dsp;
|
|
|
|
size = block->size > 4 ? 4 : block->size;
|
|
memcpy_fromio(tmp_buf, sst->addr.lpe + block->offset, size);
|
|
}
|
|
|
|
/* enable 32kB memory block - locks held by caller */
|
|
static int hsw_block_enable(struct sst_mem_block *block)
|
|
{
|
|
struct sst_dsp *sst = block->dsp;
|
|
u32 bit, val;
|
|
|
|
if (block->users++ > 0)
|
|
return 0;
|
|
|
|
dev_dbg(block->dsp->dev, " enabled block %d:%d at offset 0x%x\n",
|
|
block->type, block->index, block->offset);
|
|
|
|
/* Disable core clock gating (VDRTCTL2.DCLCGE = 0) */
|
|
val = readl(sst->addr.pci_cfg + SST_VDRTCTL2);
|
|
val &= ~SST_VDRTCL2_DCLCGE;
|
|
writel(val, sst->addr.pci_cfg + SST_VDRTCTL2);
|
|
|
|
val = readl(sst->addr.pci_cfg + SST_VDRTCTL0);
|
|
bit = hsw_block_get_bit(block);
|
|
writel(val & ~bit, sst->addr.pci_cfg + SST_VDRTCTL0);
|
|
|
|
/* wait 18 DSP clock ticks */
|
|
udelay(10);
|
|
|
|
/* Enable core clock gating (VDRTCTL2.DCLCGE = 1), delay 50 us */
|
|
val = readl(sst->addr.pci_cfg + SST_VDRTCTL2);
|
|
val |= SST_VDRTCL2_DCLCGE;
|
|
writel(val, sst->addr.pci_cfg + SST_VDRTCTL2);
|
|
|
|
udelay(50);
|
|
|
|
/*add a dummy read before the SRAM block is written, otherwise the writing may miss bytes sometimes.*/
|
|
sst_mem_block_dummy_read(block);
|
|
return 0;
|
|
}
|
|
|
|
/* disable 32kB memory block - locks held by caller */
|
|
static int hsw_block_disable(struct sst_mem_block *block)
|
|
{
|
|
struct sst_dsp *sst = block->dsp;
|
|
u32 bit, val;
|
|
|
|
if (--block->users > 0)
|
|
return 0;
|
|
|
|
dev_dbg(block->dsp->dev, " disabled block %d:%d at offset 0x%x\n",
|
|
block->type, block->index, block->offset);
|
|
|
|
/* Disable core clock gating (VDRTCTL2.DCLCGE = 0) */
|
|
val = readl(sst->addr.pci_cfg + SST_VDRTCTL2);
|
|
val &= ~SST_VDRTCL2_DCLCGE;
|
|
writel(val, sst->addr.pci_cfg + SST_VDRTCTL2);
|
|
|
|
|
|
val = readl(sst->addr.pci_cfg + SST_VDRTCTL0);
|
|
bit = hsw_block_get_bit(block);
|
|
writel(val | bit, sst->addr.pci_cfg + SST_VDRTCTL0);
|
|
|
|
/* wait 18 DSP clock ticks */
|
|
udelay(10);
|
|
|
|
/* Enable core clock gating (VDRTCTL2.DCLCGE = 1), delay 50 us */
|
|
val = readl(sst->addr.pci_cfg + SST_VDRTCTL2);
|
|
val |= SST_VDRTCL2_DCLCGE;
|
|
writel(val, sst->addr.pci_cfg + SST_VDRTCTL2);
|
|
|
|
udelay(50);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct sst_block_ops sst_hsw_ops = {
|
|
.enable = hsw_block_enable,
|
|
.disable = hsw_block_disable,
|
|
};
|
|
|
|
static int hsw_init(struct sst_dsp *sst, struct sst_pdata *pdata)
|
|
{
|
|
const struct sst_adsp_memregion *region;
|
|
struct device *dev;
|
|
int ret = -ENODEV, i, j, region_count;
|
|
u32 offset, size;
|
|
|
|
dev = sst->dma_dev;
|
|
|
|
switch (sst->id) {
|
|
case SST_DEV_ID_LYNX_POINT:
|
|
region = lp_region;
|
|
region_count = ARRAY_SIZE(lp_region);
|
|
sst->addr.iram_offset = SST_LP_IRAM_OFFSET;
|
|
sst->addr.dsp_iram_offset = SST_LPT_DSP_IRAM_OFFSET;
|
|
sst->addr.dsp_dram_offset = SST_LPT_DSP_DRAM_OFFSET;
|
|
sst->addr.shim_offset = SST_LP_SHIM_OFFSET;
|
|
break;
|
|
case SST_DEV_ID_WILDCAT_POINT:
|
|
region = wpt_region;
|
|
region_count = ARRAY_SIZE(wpt_region);
|
|
sst->addr.iram_offset = SST_WPT_IRAM_OFFSET;
|
|
sst->addr.dsp_iram_offset = SST_WPT_DSP_IRAM_OFFSET;
|
|
sst->addr.dsp_dram_offset = SST_WPT_DSP_DRAM_OFFSET;
|
|
sst->addr.shim_offset = SST_WPT_SHIM_OFFSET;
|
|
break;
|
|
default:
|
|
dev_err(dev, "error: failed to get mem resources\n");
|
|
return ret;
|
|
}
|
|
|
|
ret = hsw_acpi_resource_map(sst, pdata);
|
|
if (ret < 0) {
|
|
dev_err(dev, "error: failed to map resources\n");
|
|
return ret;
|
|
}
|
|
|
|
/* enable the DSP SHIM */
|
|
ret = hsw_set_dsp_D0(sst);
|
|
if (ret < 0) {
|
|
dev_err(dev, "error: failed to set DSP D0 and reset SHIM\n");
|
|
return ret;
|
|
}
|
|
|
|
ret = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(31));
|
|
if (ret)
|
|
return ret;
|
|
|
|
|
|
/* register DSP memory blocks - ideally we should get this from ACPI */
|
|
for (i = 0; i < region_count; i++) {
|
|
offset = region[i].start;
|
|
size = (region[i].end - region[i].start) / region[i].blocks;
|
|
|
|
/* register individual memory blocks */
|
|
for (j = 0; j < region[i].blocks; j++) {
|
|
sst_mem_block_register(sst, offset, size,
|
|
region[i].type, &sst_hsw_ops, j, sst);
|
|
offset += size;
|
|
}
|
|
}
|
|
|
|
/* set default power gating control, enable power gating control for all blocks. that is,
|
|
can't be accessed, please enable each block before accessing. */
|
|
writel(0xffffffff, sst->addr.pci_cfg + SST_VDRTCTL0);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void hsw_free(struct sst_dsp *sst)
|
|
{
|
|
sst_mem_block_unregister_all(sst);
|
|
iounmap(sst->addr.lpe);
|
|
iounmap(sst->addr.pci_cfg);
|
|
}
|
|
|
|
struct sst_ops haswell_ops = {
|
|
.reset = hsw_reset,
|
|
.boot = hsw_boot,
|
|
.stall = hsw_stall,
|
|
.wake = hsw_wake,
|
|
.sleep = hsw_sleep,
|
|
.write = sst_shim32_write,
|
|
.read = sst_shim32_read,
|
|
.write64 = sst_shim32_write64,
|
|
.read64 = sst_shim32_read64,
|
|
.ram_read = sst_memcpy_fromio_32,
|
|
.ram_write = sst_memcpy_toio_32,
|
|
.irq_handler = hsw_irq,
|
|
.init = hsw_init,
|
|
.free = hsw_free,
|
|
.parse_fw = hsw_parse_fw_image,
|
|
};
|