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14c3dec2a8
Rather than trying to wait until all possible lockers have
unlocked the lock, we now only wait until the current locker
(if any) has released the lock.
The old code was correct, but the new code works more like the x86
code and thus hopefully is more appropriate under contention.
See commit 78bff1c868 ("x86/ticketlock: Fix spin_unlock_wait()
livelock") for x86.
Signed-off-by: Chris Metcalf <cmetcalf@ezchip.com>
114 lines
3.3 KiB
C
114 lines
3.3 KiB
C
/*
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* Copyright 2011 Tilera Corporation. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation, version 2.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
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* NON INFRINGEMENT. See the GNU General Public License for
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* more details.
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*/
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#include <linux/spinlock.h>
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#include <linux/module.h>
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#include <asm/processor.h>
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#include "spinlock_common.h"
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/*
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* Read the spinlock value without allocating in our cache and without
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* causing an invalidation to another cpu with a copy of the cacheline.
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* This is important when we are spinning waiting for the lock.
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*/
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static inline u32 arch_spin_read_noalloc(void *lock)
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{
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return atomic_cmpxchg((atomic_t *)lock, -1, -1);
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}
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/*
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* Wait until the high bits (current) match my ticket.
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* If we notice the overflow bit set on entry, we clear it.
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*/
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void arch_spin_lock_slow(arch_spinlock_t *lock, u32 my_ticket)
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{
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if (unlikely(my_ticket & __ARCH_SPIN_NEXT_OVERFLOW)) {
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__insn_fetchand4(&lock->lock, ~__ARCH_SPIN_NEXT_OVERFLOW);
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my_ticket &= ~__ARCH_SPIN_NEXT_OVERFLOW;
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}
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for (;;) {
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u32 val = arch_spin_read_noalloc(lock);
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u32 delta = my_ticket - arch_spin_current(val);
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if (delta == 0)
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return;
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relax((128 / CYCLES_PER_RELAX_LOOP) * delta);
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}
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}
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EXPORT_SYMBOL(arch_spin_lock_slow);
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/*
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* Check the lock to see if it is plausible, and try to get it with cmpxchg().
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*/
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int arch_spin_trylock(arch_spinlock_t *lock)
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{
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u32 val = arch_spin_read_noalloc(lock);
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if (unlikely(arch_spin_current(val) != arch_spin_next(val)))
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return 0;
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return cmpxchg(&lock->lock, val, (val + 1) & ~__ARCH_SPIN_NEXT_OVERFLOW)
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== val;
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}
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EXPORT_SYMBOL(arch_spin_trylock);
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void arch_spin_unlock_wait(arch_spinlock_t *lock)
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{
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u32 iterations = 0;
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u32 val = READ_ONCE(lock->lock);
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u32 curr = arch_spin_current(val);
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/* Return immediately if unlocked. */
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if (arch_spin_next(val) == curr)
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return;
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/* Wait until the current locker has released the lock. */
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do {
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delay_backoff(iterations++);
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} while (arch_spin_current(READ_ONCE(lock->lock)) == curr);
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}
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EXPORT_SYMBOL(arch_spin_unlock_wait);
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/*
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* If the read lock fails due to a writer, we retry periodically
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* until the value is positive and we write our incremented reader count.
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*/
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void __read_lock_failed(arch_rwlock_t *rw)
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{
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u32 val;
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int iterations = 0;
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do {
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delay_backoff(iterations++);
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val = __insn_fetchaddgez4(&rw->lock, 1);
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} while (unlikely(arch_write_val_locked(val)));
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}
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EXPORT_SYMBOL(__read_lock_failed);
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/*
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* If we failed because there were readers, clear the "writer" bit
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* so we don't block additional readers. Otherwise, there was another
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* writer anyway, so our "fetchor" made no difference. Then wait,
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* issuing periodic fetchor instructions, till we get the lock.
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*/
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void __write_lock_failed(arch_rwlock_t *rw, u32 val)
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{
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int iterations = 0;
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do {
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if (!arch_write_val_locked(val))
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val = __insn_fetchand4(&rw->lock, ~__WRITE_LOCK_BIT);
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delay_backoff(iterations++);
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val = __insn_fetchor4(&rw->lock, __WRITE_LOCK_BIT);
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} while (val != 0);
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}
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EXPORT_SYMBOL(__write_lock_failed);
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