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The host currently writes directly in EL2 per-CPU data sections from the PMU code when running in nVHE. In preparation for unmapping the EL2 sections from the host stage 2, disable PMU support in protected mode as we currently do not have a use-case for it. Acked-by: Will Deacon <will@kernel.org> Signed-off-by: Quentin Perret <qperret@google.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20210319100146.1149909-38-qperret@google.com
206 lines
5.2 KiB
C
206 lines
5.2 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright 2019 Arm Limited
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* Author: Andrew Murray <Andrew.Murray@arm.com>
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*/
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#include <linux/kvm_host.h>
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#include <linux/perf_event.h>
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#include <asm/kvm_hyp.h>
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/*
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* Given the perf event attributes and system type, determine
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* if we are going to need to switch counters at guest entry/exit.
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*/
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static bool kvm_pmu_switch_needed(struct perf_event_attr *attr)
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{
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/**
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* With VHE the guest kernel runs at EL1 and the host at EL2,
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* where user (EL0) is excluded then we have no reason to switch
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* counters.
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*/
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if (has_vhe() && attr->exclude_user)
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return false;
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/* Only switch if attributes are different */
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return (attr->exclude_host != attr->exclude_guest);
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}
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/*
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* Add events to track that we may want to switch at guest entry/exit
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* time.
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*/
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void kvm_set_pmu_events(u32 set, struct perf_event_attr *attr)
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{
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struct kvm_host_data *ctx = this_cpu_ptr_hyp_sym(kvm_host_data);
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if (!kvm_arm_support_pmu_v3() || !ctx || !kvm_pmu_switch_needed(attr))
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return;
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if (!attr->exclude_host)
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ctx->pmu_events.events_host |= set;
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if (!attr->exclude_guest)
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ctx->pmu_events.events_guest |= set;
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}
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/*
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* Stop tracking events
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*/
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void kvm_clr_pmu_events(u32 clr)
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{
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struct kvm_host_data *ctx = this_cpu_ptr_hyp_sym(kvm_host_data);
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if (!kvm_arm_support_pmu_v3() || !ctx)
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return;
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ctx->pmu_events.events_host &= ~clr;
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ctx->pmu_events.events_guest &= ~clr;
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}
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#define PMEVTYPER_READ_CASE(idx) \
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case idx: \
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return read_sysreg(pmevtyper##idx##_el0)
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#define PMEVTYPER_WRITE_CASE(idx) \
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case idx: \
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write_sysreg(val, pmevtyper##idx##_el0); \
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break
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#define PMEVTYPER_CASES(readwrite) \
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PMEVTYPER_##readwrite##_CASE(0); \
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PMEVTYPER_##readwrite##_CASE(1); \
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PMEVTYPER_##readwrite##_CASE(2); \
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PMEVTYPER_##readwrite##_CASE(3); \
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PMEVTYPER_##readwrite##_CASE(4); \
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PMEVTYPER_##readwrite##_CASE(5); \
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PMEVTYPER_##readwrite##_CASE(6); \
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PMEVTYPER_##readwrite##_CASE(7); \
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PMEVTYPER_##readwrite##_CASE(8); \
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PMEVTYPER_##readwrite##_CASE(9); \
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PMEVTYPER_##readwrite##_CASE(10); \
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PMEVTYPER_##readwrite##_CASE(11); \
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PMEVTYPER_##readwrite##_CASE(12); \
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PMEVTYPER_##readwrite##_CASE(13); \
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PMEVTYPER_##readwrite##_CASE(14); \
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PMEVTYPER_##readwrite##_CASE(15); \
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PMEVTYPER_##readwrite##_CASE(16); \
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PMEVTYPER_##readwrite##_CASE(17); \
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PMEVTYPER_##readwrite##_CASE(18); \
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PMEVTYPER_##readwrite##_CASE(19); \
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PMEVTYPER_##readwrite##_CASE(20); \
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PMEVTYPER_##readwrite##_CASE(21); \
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PMEVTYPER_##readwrite##_CASE(22); \
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PMEVTYPER_##readwrite##_CASE(23); \
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PMEVTYPER_##readwrite##_CASE(24); \
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PMEVTYPER_##readwrite##_CASE(25); \
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PMEVTYPER_##readwrite##_CASE(26); \
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PMEVTYPER_##readwrite##_CASE(27); \
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PMEVTYPER_##readwrite##_CASE(28); \
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PMEVTYPER_##readwrite##_CASE(29); \
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PMEVTYPER_##readwrite##_CASE(30)
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/*
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* Read a value direct from PMEVTYPER<idx> where idx is 0-30
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* or PMCCFILTR_EL0 where idx is ARMV8_PMU_CYCLE_IDX (31).
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*/
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static u64 kvm_vcpu_pmu_read_evtype_direct(int idx)
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{
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switch (idx) {
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PMEVTYPER_CASES(READ);
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case ARMV8_PMU_CYCLE_IDX:
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return read_sysreg(pmccfiltr_el0);
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default:
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WARN_ON(1);
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}
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return 0;
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}
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/*
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* Write a value direct to PMEVTYPER<idx> where idx is 0-30
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* or PMCCFILTR_EL0 where idx is ARMV8_PMU_CYCLE_IDX (31).
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*/
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static void kvm_vcpu_pmu_write_evtype_direct(int idx, u32 val)
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{
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switch (idx) {
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PMEVTYPER_CASES(WRITE);
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case ARMV8_PMU_CYCLE_IDX:
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write_sysreg(val, pmccfiltr_el0);
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break;
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default:
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WARN_ON(1);
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}
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}
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/*
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* Modify ARMv8 PMU events to include EL0 counting
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*/
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static void kvm_vcpu_pmu_enable_el0(unsigned long events)
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{
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u64 typer;
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u32 counter;
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for_each_set_bit(counter, &events, 32) {
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typer = kvm_vcpu_pmu_read_evtype_direct(counter);
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typer &= ~ARMV8_PMU_EXCLUDE_EL0;
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kvm_vcpu_pmu_write_evtype_direct(counter, typer);
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}
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}
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/*
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* Modify ARMv8 PMU events to exclude EL0 counting
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*/
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static void kvm_vcpu_pmu_disable_el0(unsigned long events)
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{
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u64 typer;
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u32 counter;
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for_each_set_bit(counter, &events, 32) {
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typer = kvm_vcpu_pmu_read_evtype_direct(counter);
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typer |= ARMV8_PMU_EXCLUDE_EL0;
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kvm_vcpu_pmu_write_evtype_direct(counter, typer);
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}
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}
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/*
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* On VHE ensure that only guest events have EL0 counting enabled.
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* This is called from both vcpu_{load,put} and the sysreg handling.
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* Since the latter is preemptible, special care must be taken to
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* disable preemption.
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*/
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void kvm_vcpu_pmu_restore_guest(struct kvm_vcpu *vcpu)
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{
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struct kvm_host_data *host;
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u32 events_guest, events_host;
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if (!kvm_arm_support_pmu_v3() || !has_vhe())
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return;
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preempt_disable();
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host = this_cpu_ptr_hyp_sym(kvm_host_data);
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events_guest = host->pmu_events.events_guest;
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events_host = host->pmu_events.events_host;
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kvm_vcpu_pmu_enable_el0(events_guest);
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kvm_vcpu_pmu_disable_el0(events_host);
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preempt_enable();
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}
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/*
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* On VHE ensure that only host events have EL0 counting enabled
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*/
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void kvm_vcpu_pmu_restore_host(struct kvm_vcpu *vcpu)
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{
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struct kvm_host_data *host;
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u32 events_guest, events_host;
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if (!kvm_arm_support_pmu_v3() || !has_vhe())
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return;
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host = this_cpu_ptr_hyp_sym(kvm_host_data);
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events_guest = host->pmu_events.events_guest;
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events_host = host->pmu_events.events_host;
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kvm_vcpu_pmu_enable_el0(events_host);
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kvm_vcpu_pmu_disable_el0(events_guest);
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}
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