mirror of
https://mirrors.bfsu.edu.cn/git/linux.git
synced 2024-12-09 20:14:09 +08:00
211a22ce08
Together with new fixes update driver version and extend copyright dates ranges. Signed-off-by: Maciej Sosnowski <maciej.sosnowski@intel.com> Signed-off-by: Shannon Nelson <shannon.nelson@intel.com> Acked-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
682 lines
17 KiB
C
682 lines
17 KiB
C
/*
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* Intel I/OAT DMA Linux driver
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* Copyright(c) 2007 - 2009 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* The full GNU General Public License is included in this distribution in
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* the file called "COPYING".
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*
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*/
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/smp.h>
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#include <linux/interrupt.h>
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#include <linux/dca.h>
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/* either a kernel change is needed, or we need something like this in kernel */
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#ifndef CONFIG_SMP
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#include <asm/smp.h>
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#undef cpu_physical_id
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#define cpu_physical_id(cpu) (cpuid_ebx(1) >> 24)
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#endif
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#include "ioatdma.h"
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#include "ioatdma_registers.h"
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/*
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* Bit 7 of a tag map entry is the "valid" bit, if it is set then bits 0:6
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* contain the bit number of the APIC ID to map into the DCA tag. If the valid
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* bit is not set, then the value must be 0 or 1 and defines the bit in the tag.
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*/
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#define DCA_TAG_MAP_VALID 0x80
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#define DCA3_TAG_MAP_BIT_TO_INV 0x80
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#define DCA3_TAG_MAP_BIT_TO_SEL 0x40
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#define DCA3_TAG_MAP_LITERAL_VAL 0x1
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#define DCA_TAG_MAP_MASK 0xDF
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/* expected tag map bytes for I/OAT ver.2 */
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#define DCA2_TAG_MAP_BYTE0 0x80
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#define DCA2_TAG_MAP_BYTE1 0x0
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#define DCA2_TAG_MAP_BYTE2 0x81
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#define DCA2_TAG_MAP_BYTE3 0x82
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#define DCA2_TAG_MAP_BYTE4 0x82
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/* verify if tag map matches expected values */
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static inline int dca2_tag_map_valid(u8 *tag_map)
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{
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return ((tag_map[0] == DCA2_TAG_MAP_BYTE0) &&
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(tag_map[1] == DCA2_TAG_MAP_BYTE1) &&
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(tag_map[2] == DCA2_TAG_MAP_BYTE2) &&
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(tag_map[3] == DCA2_TAG_MAP_BYTE3) &&
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(tag_map[4] == DCA2_TAG_MAP_BYTE4));
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}
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/*
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* "Legacy" DCA systems do not implement the DCA register set in the
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* I/OAT device. Software needs direct support for their tag mappings.
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*/
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#define APICID_BIT(x) (DCA_TAG_MAP_VALID | (x))
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#define IOAT_TAG_MAP_LEN 8
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static u8 ioat_tag_map_BNB[IOAT_TAG_MAP_LEN] = {
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1, APICID_BIT(1), APICID_BIT(2), APICID_BIT(2), };
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static u8 ioat_tag_map_SCNB[IOAT_TAG_MAP_LEN] = {
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1, APICID_BIT(1), APICID_BIT(2), APICID_BIT(2), };
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static u8 ioat_tag_map_CNB[IOAT_TAG_MAP_LEN] = {
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1, APICID_BIT(1), APICID_BIT(3), APICID_BIT(4), APICID_BIT(2), };
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static u8 ioat_tag_map_UNISYS[IOAT_TAG_MAP_LEN] = { 0 };
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/* pack PCI B/D/F into a u16 */
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static inline u16 dcaid_from_pcidev(struct pci_dev *pci)
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{
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return (pci->bus->number << 8) | pci->devfn;
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}
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static int dca_enabled_in_bios(struct pci_dev *pdev)
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{
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/* CPUID level 9 returns DCA configuration */
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/* Bit 0 indicates DCA enabled by the BIOS */
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unsigned long cpuid_level_9;
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int res;
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cpuid_level_9 = cpuid_eax(9);
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res = test_bit(0, &cpuid_level_9);
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if (!res)
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dev_err(&pdev->dev, "DCA is disabled in BIOS\n");
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return res;
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}
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static int system_has_dca_enabled(struct pci_dev *pdev)
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{
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if (boot_cpu_has(X86_FEATURE_DCA))
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return dca_enabled_in_bios(pdev);
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dev_err(&pdev->dev, "boot cpu doesn't have X86_FEATURE_DCA\n");
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return 0;
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}
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struct ioat_dca_slot {
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struct pci_dev *pdev; /* requester device */
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u16 rid; /* requester id, as used by IOAT */
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};
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#define IOAT_DCA_MAX_REQ 6
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#define IOAT3_DCA_MAX_REQ 2
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struct ioat_dca_priv {
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void __iomem *iobase;
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void __iomem *dca_base;
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int max_requesters;
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int requester_count;
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u8 tag_map[IOAT_TAG_MAP_LEN];
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struct ioat_dca_slot req_slots[0];
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};
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/* 5000 series chipset DCA Port Requester ID Table Entry Format
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* [15:8] PCI-Express Bus Number
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* [7:3] PCI-Express Device Number
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* [2:0] PCI-Express Function Number
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*
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* 5000 series chipset DCA control register format
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* [7:1] Reserved (0)
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* [0] Ignore Function Number
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*/
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static int ioat_dca_add_requester(struct dca_provider *dca, struct device *dev)
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{
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struct ioat_dca_priv *ioatdca = dca_priv(dca);
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struct pci_dev *pdev;
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int i;
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u16 id;
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/* This implementation only supports PCI-Express */
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if (dev->bus != &pci_bus_type)
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return -ENODEV;
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pdev = to_pci_dev(dev);
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id = dcaid_from_pcidev(pdev);
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if (ioatdca->requester_count == ioatdca->max_requesters)
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return -ENODEV;
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for (i = 0; i < ioatdca->max_requesters; i++) {
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if (ioatdca->req_slots[i].pdev == NULL) {
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/* found an empty slot */
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ioatdca->requester_count++;
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ioatdca->req_slots[i].pdev = pdev;
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ioatdca->req_slots[i].rid = id;
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writew(id, ioatdca->dca_base + (i * 4));
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/* make sure the ignore function bit is off */
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writeb(0, ioatdca->dca_base + (i * 4) + 2);
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return i;
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}
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}
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/* Error, ioatdma->requester_count is out of whack */
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return -EFAULT;
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}
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static int ioat_dca_remove_requester(struct dca_provider *dca,
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struct device *dev)
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{
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struct ioat_dca_priv *ioatdca = dca_priv(dca);
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struct pci_dev *pdev;
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int i;
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/* This implementation only supports PCI-Express */
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if (dev->bus != &pci_bus_type)
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return -ENODEV;
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pdev = to_pci_dev(dev);
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for (i = 0; i < ioatdca->max_requesters; i++) {
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if (ioatdca->req_slots[i].pdev == pdev) {
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writew(0, ioatdca->dca_base + (i * 4));
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ioatdca->req_slots[i].pdev = NULL;
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ioatdca->req_slots[i].rid = 0;
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ioatdca->requester_count--;
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return i;
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}
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}
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return -ENODEV;
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}
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static u8 ioat_dca_get_tag(struct dca_provider *dca,
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struct device *dev,
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int cpu)
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{
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struct ioat_dca_priv *ioatdca = dca_priv(dca);
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int i, apic_id, bit, value;
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u8 entry, tag;
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tag = 0;
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apic_id = cpu_physical_id(cpu);
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for (i = 0; i < IOAT_TAG_MAP_LEN; i++) {
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entry = ioatdca->tag_map[i];
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if (entry & DCA_TAG_MAP_VALID) {
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bit = entry & ~DCA_TAG_MAP_VALID;
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value = (apic_id & (1 << bit)) ? 1 : 0;
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} else {
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value = entry ? 1 : 0;
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}
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tag |= (value << i);
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}
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return tag;
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}
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static int ioat_dca_dev_managed(struct dca_provider *dca,
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struct device *dev)
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{
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struct ioat_dca_priv *ioatdca = dca_priv(dca);
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struct pci_dev *pdev;
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int i;
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pdev = to_pci_dev(dev);
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for (i = 0; i < ioatdca->max_requesters; i++) {
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if (ioatdca->req_slots[i].pdev == pdev)
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return 1;
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}
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return 0;
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}
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static struct dca_ops ioat_dca_ops = {
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.add_requester = ioat_dca_add_requester,
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.remove_requester = ioat_dca_remove_requester,
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.get_tag = ioat_dca_get_tag,
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.dev_managed = ioat_dca_dev_managed,
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};
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struct dca_provider *ioat_dca_init(struct pci_dev *pdev, void __iomem *iobase)
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{
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struct dca_provider *dca;
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struct ioat_dca_priv *ioatdca;
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u8 *tag_map = NULL;
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int i;
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int err;
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u8 version;
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u8 max_requesters;
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if (!system_has_dca_enabled(pdev))
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return NULL;
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/* I/OAT v1 systems must have a known tag_map to support DCA */
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switch (pdev->vendor) {
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case PCI_VENDOR_ID_INTEL:
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switch (pdev->device) {
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case PCI_DEVICE_ID_INTEL_IOAT:
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tag_map = ioat_tag_map_BNB;
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break;
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case PCI_DEVICE_ID_INTEL_IOAT_CNB:
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tag_map = ioat_tag_map_CNB;
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break;
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case PCI_DEVICE_ID_INTEL_IOAT_SCNB:
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tag_map = ioat_tag_map_SCNB;
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break;
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}
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break;
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case PCI_VENDOR_ID_UNISYS:
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switch (pdev->device) {
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case PCI_DEVICE_ID_UNISYS_DMA_DIRECTOR:
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tag_map = ioat_tag_map_UNISYS;
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break;
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}
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break;
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}
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if (tag_map == NULL)
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return NULL;
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version = readb(iobase + IOAT_VER_OFFSET);
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if (version == IOAT_VER_3_0)
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max_requesters = IOAT3_DCA_MAX_REQ;
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else
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max_requesters = IOAT_DCA_MAX_REQ;
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dca = alloc_dca_provider(&ioat_dca_ops,
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sizeof(*ioatdca) +
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(sizeof(struct ioat_dca_slot) * max_requesters));
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if (!dca)
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return NULL;
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ioatdca = dca_priv(dca);
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ioatdca->max_requesters = max_requesters;
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ioatdca->dca_base = iobase + 0x54;
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/* copy over the APIC ID to DCA tag mapping */
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for (i = 0; i < IOAT_TAG_MAP_LEN; i++)
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ioatdca->tag_map[i] = tag_map[i];
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err = register_dca_provider(dca, &pdev->dev);
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if (err) {
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free_dca_provider(dca);
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return NULL;
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}
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return dca;
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}
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static int ioat2_dca_add_requester(struct dca_provider *dca, struct device *dev)
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{
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struct ioat_dca_priv *ioatdca = dca_priv(dca);
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struct pci_dev *pdev;
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int i;
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u16 id;
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u16 global_req_table;
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/* This implementation only supports PCI-Express */
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if (dev->bus != &pci_bus_type)
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return -ENODEV;
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pdev = to_pci_dev(dev);
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id = dcaid_from_pcidev(pdev);
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if (ioatdca->requester_count == ioatdca->max_requesters)
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return -ENODEV;
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for (i = 0; i < ioatdca->max_requesters; i++) {
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if (ioatdca->req_slots[i].pdev == NULL) {
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/* found an empty slot */
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ioatdca->requester_count++;
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ioatdca->req_slots[i].pdev = pdev;
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ioatdca->req_slots[i].rid = id;
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global_req_table =
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readw(ioatdca->dca_base + IOAT_DCA_GREQID_OFFSET);
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writel(id | IOAT_DCA_GREQID_VALID,
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ioatdca->iobase + global_req_table + (i * 4));
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return i;
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}
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}
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/* Error, ioatdma->requester_count is out of whack */
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return -EFAULT;
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}
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static int ioat2_dca_remove_requester(struct dca_provider *dca,
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struct device *dev)
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{
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struct ioat_dca_priv *ioatdca = dca_priv(dca);
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struct pci_dev *pdev;
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int i;
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u16 global_req_table;
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/* This implementation only supports PCI-Express */
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if (dev->bus != &pci_bus_type)
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return -ENODEV;
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pdev = to_pci_dev(dev);
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for (i = 0; i < ioatdca->max_requesters; i++) {
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if (ioatdca->req_slots[i].pdev == pdev) {
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global_req_table =
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readw(ioatdca->dca_base + IOAT_DCA_GREQID_OFFSET);
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writel(0, ioatdca->iobase + global_req_table + (i * 4));
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ioatdca->req_slots[i].pdev = NULL;
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ioatdca->req_slots[i].rid = 0;
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ioatdca->requester_count--;
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return i;
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}
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}
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return -ENODEV;
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}
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static u8 ioat2_dca_get_tag(struct dca_provider *dca,
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struct device *dev,
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int cpu)
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{
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u8 tag;
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tag = ioat_dca_get_tag(dca, dev, cpu);
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tag = (~tag) & 0x1F;
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return tag;
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}
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static struct dca_ops ioat2_dca_ops = {
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.add_requester = ioat2_dca_add_requester,
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.remove_requester = ioat2_dca_remove_requester,
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.get_tag = ioat2_dca_get_tag,
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.dev_managed = ioat_dca_dev_managed,
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};
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static int ioat2_dca_count_dca_slots(void __iomem *iobase, u16 dca_offset)
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{
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int slots = 0;
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u32 req;
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u16 global_req_table;
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global_req_table = readw(iobase + dca_offset + IOAT_DCA_GREQID_OFFSET);
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if (global_req_table == 0)
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return 0;
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do {
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req = readl(iobase + global_req_table + (slots * sizeof(u32)));
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slots++;
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} while ((req & IOAT_DCA_GREQID_LASTID) == 0);
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return slots;
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}
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struct dca_provider *ioat2_dca_init(struct pci_dev *pdev, void __iomem *iobase)
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{
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struct dca_provider *dca;
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struct ioat_dca_priv *ioatdca;
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int slots;
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int i;
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int err;
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u32 tag_map;
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u16 dca_offset;
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u16 csi_fsb_control;
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u16 pcie_control;
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u8 bit;
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if (!system_has_dca_enabled(pdev))
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return NULL;
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dca_offset = readw(iobase + IOAT_DCAOFFSET_OFFSET);
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if (dca_offset == 0)
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return NULL;
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slots = ioat2_dca_count_dca_slots(iobase, dca_offset);
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if (slots == 0)
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return NULL;
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dca = alloc_dca_provider(&ioat2_dca_ops,
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sizeof(*ioatdca)
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+ (sizeof(struct ioat_dca_slot) * slots));
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if (!dca)
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return NULL;
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ioatdca = dca_priv(dca);
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ioatdca->iobase = iobase;
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ioatdca->dca_base = iobase + dca_offset;
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ioatdca->max_requesters = slots;
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/* some bios might not know to turn these on */
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csi_fsb_control = readw(ioatdca->dca_base + IOAT_FSB_CAP_ENABLE_OFFSET);
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if ((csi_fsb_control & IOAT_FSB_CAP_ENABLE_PREFETCH) == 0) {
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csi_fsb_control |= IOAT_FSB_CAP_ENABLE_PREFETCH;
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writew(csi_fsb_control,
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ioatdca->dca_base + IOAT_FSB_CAP_ENABLE_OFFSET);
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}
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pcie_control = readw(ioatdca->dca_base + IOAT_PCI_CAP_ENABLE_OFFSET);
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if ((pcie_control & IOAT_PCI_CAP_ENABLE_MEMWR) == 0) {
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pcie_control |= IOAT_PCI_CAP_ENABLE_MEMWR;
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writew(pcie_control,
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ioatdca->dca_base + IOAT_PCI_CAP_ENABLE_OFFSET);
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}
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/* TODO version, compatibility and configuration checks */
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/* copy out the APIC to DCA tag map */
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tag_map = readl(ioatdca->dca_base + IOAT_APICID_TAG_MAP_OFFSET);
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for (i = 0; i < 5; i++) {
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bit = (tag_map >> (4 * i)) & 0x0f;
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if (bit < 8)
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ioatdca->tag_map[i] = bit | DCA_TAG_MAP_VALID;
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else
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ioatdca->tag_map[i] = 0;
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}
|
|
|
|
if (!dca2_tag_map_valid(ioatdca->tag_map)) {
|
|
dev_err(&pdev->dev, "APICID_TAG_MAP set incorrectly by BIOS, "
|
|
"disabling DCA\n");
|
|
free_dca_provider(dca);
|
|
return NULL;
|
|
}
|
|
|
|
err = register_dca_provider(dca, &pdev->dev);
|
|
if (err) {
|
|
free_dca_provider(dca);
|
|
return NULL;
|
|
}
|
|
|
|
return dca;
|
|
}
|
|
|
|
static int ioat3_dca_add_requester(struct dca_provider *dca, struct device *dev)
|
|
{
|
|
struct ioat_dca_priv *ioatdca = dca_priv(dca);
|
|
struct pci_dev *pdev;
|
|
int i;
|
|
u16 id;
|
|
u16 global_req_table;
|
|
|
|
/* This implementation only supports PCI-Express */
|
|
if (dev->bus != &pci_bus_type)
|
|
return -ENODEV;
|
|
pdev = to_pci_dev(dev);
|
|
id = dcaid_from_pcidev(pdev);
|
|
|
|
if (ioatdca->requester_count == ioatdca->max_requesters)
|
|
return -ENODEV;
|
|
|
|
for (i = 0; i < ioatdca->max_requesters; i++) {
|
|
if (ioatdca->req_slots[i].pdev == NULL) {
|
|
/* found an empty slot */
|
|
ioatdca->requester_count++;
|
|
ioatdca->req_slots[i].pdev = pdev;
|
|
ioatdca->req_slots[i].rid = id;
|
|
global_req_table =
|
|
readw(ioatdca->dca_base + IOAT3_DCA_GREQID_OFFSET);
|
|
writel(id | IOAT_DCA_GREQID_VALID,
|
|
ioatdca->iobase + global_req_table + (i * 4));
|
|
return i;
|
|
}
|
|
}
|
|
/* Error, ioatdma->requester_count is out of whack */
|
|
return -EFAULT;
|
|
}
|
|
|
|
static int ioat3_dca_remove_requester(struct dca_provider *dca,
|
|
struct device *dev)
|
|
{
|
|
struct ioat_dca_priv *ioatdca = dca_priv(dca);
|
|
struct pci_dev *pdev;
|
|
int i;
|
|
u16 global_req_table;
|
|
|
|
/* This implementation only supports PCI-Express */
|
|
if (dev->bus != &pci_bus_type)
|
|
return -ENODEV;
|
|
pdev = to_pci_dev(dev);
|
|
|
|
for (i = 0; i < ioatdca->max_requesters; i++) {
|
|
if (ioatdca->req_slots[i].pdev == pdev) {
|
|
global_req_table =
|
|
readw(ioatdca->dca_base + IOAT3_DCA_GREQID_OFFSET);
|
|
writel(0, ioatdca->iobase + global_req_table + (i * 4));
|
|
ioatdca->req_slots[i].pdev = NULL;
|
|
ioatdca->req_slots[i].rid = 0;
|
|
ioatdca->requester_count--;
|
|
return i;
|
|
}
|
|
}
|
|
return -ENODEV;
|
|
}
|
|
|
|
static u8 ioat3_dca_get_tag(struct dca_provider *dca,
|
|
struct device *dev,
|
|
int cpu)
|
|
{
|
|
u8 tag;
|
|
|
|
struct ioat_dca_priv *ioatdca = dca_priv(dca);
|
|
int i, apic_id, bit, value;
|
|
u8 entry;
|
|
|
|
tag = 0;
|
|
apic_id = cpu_physical_id(cpu);
|
|
|
|
for (i = 0; i < IOAT_TAG_MAP_LEN; i++) {
|
|
entry = ioatdca->tag_map[i];
|
|
if (entry & DCA3_TAG_MAP_BIT_TO_SEL) {
|
|
bit = entry &
|
|
~(DCA3_TAG_MAP_BIT_TO_SEL | DCA3_TAG_MAP_BIT_TO_INV);
|
|
value = (apic_id & (1 << bit)) ? 1 : 0;
|
|
} else if (entry & DCA3_TAG_MAP_BIT_TO_INV) {
|
|
bit = entry & ~DCA3_TAG_MAP_BIT_TO_INV;
|
|
value = (apic_id & (1 << bit)) ? 0 : 1;
|
|
} else {
|
|
value = (entry & DCA3_TAG_MAP_LITERAL_VAL) ? 1 : 0;
|
|
}
|
|
tag |= (value << i);
|
|
}
|
|
|
|
return tag;
|
|
}
|
|
|
|
static struct dca_ops ioat3_dca_ops = {
|
|
.add_requester = ioat3_dca_add_requester,
|
|
.remove_requester = ioat3_dca_remove_requester,
|
|
.get_tag = ioat3_dca_get_tag,
|
|
.dev_managed = ioat_dca_dev_managed,
|
|
};
|
|
|
|
static int ioat3_dca_count_dca_slots(void *iobase, u16 dca_offset)
|
|
{
|
|
int slots = 0;
|
|
u32 req;
|
|
u16 global_req_table;
|
|
|
|
global_req_table = readw(iobase + dca_offset + IOAT3_DCA_GREQID_OFFSET);
|
|
if (global_req_table == 0)
|
|
return 0;
|
|
|
|
do {
|
|
req = readl(iobase + global_req_table + (slots * sizeof(u32)));
|
|
slots++;
|
|
} while ((req & IOAT_DCA_GREQID_LASTID) == 0);
|
|
|
|
return slots;
|
|
}
|
|
|
|
struct dca_provider *ioat3_dca_init(struct pci_dev *pdev, void __iomem *iobase)
|
|
{
|
|
struct dca_provider *dca;
|
|
struct ioat_dca_priv *ioatdca;
|
|
int slots;
|
|
int i;
|
|
int err;
|
|
u16 dca_offset;
|
|
u16 csi_fsb_control;
|
|
u16 pcie_control;
|
|
u8 bit;
|
|
|
|
union {
|
|
u64 full;
|
|
struct {
|
|
u32 low;
|
|
u32 high;
|
|
};
|
|
} tag_map;
|
|
|
|
if (!system_has_dca_enabled(pdev))
|
|
return NULL;
|
|
|
|
dca_offset = readw(iobase + IOAT_DCAOFFSET_OFFSET);
|
|
if (dca_offset == 0)
|
|
return NULL;
|
|
|
|
slots = ioat3_dca_count_dca_slots(iobase, dca_offset);
|
|
if (slots == 0)
|
|
return NULL;
|
|
|
|
dca = alloc_dca_provider(&ioat3_dca_ops,
|
|
sizeof(*ioatdca)
|
|
+ (sizeof(struct ioat_dca_slot) * slots));
|
|
if (!dca)
|
|
return NULL;
|
|
|
|
ioatdca = dca_priv(dca);
|
|
ioatdca->iobase = iobase;
|
|
ioatdca->dca_base = iobase + dca_offset;
|
|
ioatdca->max_requesters = slots;
|
|
|
|
/* some bios might not know to turn these on */
|
|
csi_fsb_control = readw(ioatdca->dca_base + IOAT3_CSI_CONTROL_OFFSET);
|
|
if ((csi_fsb_control & IOAT3_CSI_CONTROL_PREFETCH) == 0) {
|
|
csi_fsb_control |= IOAT3_CSI_CONTROL_PREFETCH;
|
|
writew(csi_fsb_control,
|
|
ioatdca->dca_base + IOAT3_CSI_CONTROL_OFFSET);
|
|
}
|
|
pcie_control = readw(ioatdca->dca_base + IOAT3_PCI_CONTROL_OFFSET);
|
|
if ((pcie_control & IOAT3_PCI_CONTROL_MEMWR) == 0) {
|
|
pcie_control |= IOAT3_PCI_CONTROL_MEMWR;
|
|
writew(pcie_control,
|
|
ioatdca->dca_base + IOAT3_PCI_CONTROL_OFFSET);
|
|
}
|
|
|
|
|
|
/* TODO version, compatibility and configuration checks */
|
|
|
|
/* copy out the APIC to DCA tag map */
|
|
tag_map.low =
|
|
readl(ioatdca->dca_base + IOAT3_APICID_TAG_MAP_OFFSET_LOW);
|
|
tag_map.high =
|
|
readl(ioatdca->dca_base + IOAT3_APICID_TAG_MAP_OFFSET_HIGH);
|
|
for (i = 0; i < 8; i++) {
|
|
bit = tag_map.full >> (8 * i);
|
|
ioatdca->tag_map[i] = bit & DCA_TAG_MAP_MASK;
|
|
}
|
|
|
|
err = register_dca_provider(dca, &pdev->dev);
|
|
if (err) {
|
|
free_dca_provider(dca);
|
|
return NULL;
|
|
}
|
|
|
|
return dca;
|
|
}
|