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d9de451989
This patch adds a cyclic DMA interface to the DW DMA driver. This is very useful if you want to use the DMA controller in combination with a sound device which uses cyclic buffers. Using a DMA channel for cyclic DMA will disable the possibility to use it as a normal DMA engine until the user calls the cyclic free function on the DMA channel. Also a cyclic DMA list can not be prepared if the channel is already active. Signed-off-by: Hans-Christian Egtvedt <hans-christian.egtvedt@atmel.com> Acked-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com> Acked-by: Maciej Sosnowski <maciej.sosnowski@intel.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
1446 lines
37 KiB
C
1446 lines
37 KiB
C
/*
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* Driver for the Synopsys DesignWare DMA Controller (aka DMACA on
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* AVR32 systems.)
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*
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* Copyright (C) 2007-2008 Atmel Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/dmaengine.h>
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#include <linux/dma-mapping.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/mm.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include "dw_dmac_regs.h"
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/*
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* This supports the Synopsys "DesignWare AHB Central DMA Controller",
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* (DW_ahb_dmac) which is used with various AMBA 2.0 systems (not all
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* of which use ARM any more). See the "Databook" from Synopsys for
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* information beyond what licensees probably provide.
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*
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* The driver has currently been tested only with the Atmel AT32AP7000,
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* which does not support descriptor writeback.
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*/
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/* NOTE: DMS+SMS is system-specific. We should get this information
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* from the platform code somehow.
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*/
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#define DWC_DEFAULT_CTLLO (DWC_CTLL_DST_MSIZE(0) \
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| DWC_CTLL_SRC_MSIZE(0) \
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| DWC_CTLL_DMS(0) \
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| DWC_CTLL_SMS(1) \
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| DWC_CTLL_LLP_D_EN \
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| DWC_CTLL_LLP_S_EN)
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/*
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* This is configuration-dependent and usually a funny size like 4095.
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* Let's round it down to the nearest power of two.
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*
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* Note that this is a transfer count, i.e. if we transfer 32-bit
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* words, we can do 8192 bytes per descriptor.
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*
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* This parameter is also system-specific.
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*/
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#define DWC_MAX_COUNT 2048U
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/*
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* Number of descriptors to allocate for each channel. This should be
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* made configurable somehow; preferably, the clients (at least the
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* ones using slave transfers) should be able to give us a hint.
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*/
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#define NR_DESCS_PER_CHANNEL 64
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/*----------------------------------------------------------------------*/
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/*
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* Because we're not relying on writeback from the controller (it may not
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* even be configured into the core!) we don't need to use dma_pool. These
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* descriptors -- and associated data -- are cacheable. We do need to make
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* sure their dcache entries are written back before handing them off to
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* the controller, though.
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*/
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static struct device *chan2dev(struct dma_chan *chan)
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{
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return &chan->dev->device;
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}
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static struct device *chan2parent(struct dma_chan *chan)
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{
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return chan->dev->device.parent;
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}
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static struct dw_desc *dwc_first_active(struct dw_dma_chan *dwc)
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{
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return list_entry(dwc->active_list.next, struct dw_desc, desc_node);
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}
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static struct dw_desc *dwc_first_queued(struct dw_dma_chan *dwc)
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{
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return list_entry(dwc->queue.next, struct dw_desc, desc_node);
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}
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static struct dw_desc *dwc_desc_get(struct dw_dma_chan *dwc)
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{
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struct dw_desc *desc, *_desc;
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struct dw_desc *ret = NULL;
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unsigned int i = 0;
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spin_lock_bh(&dwc->lock);
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list_for_each_entry_safe(desc, _desc, &dwc->free_list, desc_node) {
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if (async_tx_test_ack(&desc->txd)) {
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list_del(&desc->desc_node);
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ret = desc;
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break;
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}
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dev_dbg(chan2dev(&dwc->chan), "desc %p not ACKed\n", desc);
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i++;
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}
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spin_unlock_bh(&dwc->lock);
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dev_vdbg(chan2dev(&dwc->chan), "scanned %u descriptors on freelist\n", i);
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return ret;
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}
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static void dwc_sync_desc_for_cpu(struct dw_dma_chan *dwc, struct dw_desc *desc)
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{
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struct dw_desc *child;
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list_for_each_entry(child, &desc->txd.tx_list, desc_node)
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dma_sync_single_for_cpu(chan2parent(&dwc->chan),
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child->txd.phys, sizeof(child->lli),
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DMA_TO_DEVICE);
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dma_sync_single_for_cpu(chan2parent(&dwc->chan),
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desc->txd.phys, sizeof(desc->lli),
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DMA_TO_DEVICE);
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}
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/*
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* Move a descriptor, including any children, to the free list.
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* `desc' must not be on any lists.
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*/
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static void dwc_desc_put(struct dw_dma_chan *dwc, struct dw_desc *desc)
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{
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if (desc) {
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struct dw_desc *child;
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dwc_sync_desc_for_cpu(dwc, desc);
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spin_lock_bh(&dwc->lock);
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list_for_each_entry(child, &desc->txd.tx_list, desc_node)
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dev_vdbg(chan2dev(&dwc->chan),
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"moving child desc %p to freelist\n",
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child);
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list_splice_init(&desc->txd.tx_list, &dwc->free_list);
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dev_vdbg(chan2dev(&dwc->chan), "moving desc %p to freelist\n", desc);
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list_add(&desc->desc_node, &dwc->free_list);
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spin_unlock_bh(&dwc->lock);
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}
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}
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/* Called with dwc->lock held and bh disabled */
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static dma_cookie_t
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dwc_assign_cookie(struct dw_dma_chan *dwc, struct dw_desc *desc)
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{
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dma_cookie_t cookie = dwc->chan.cookie;
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if (++cookie < 0)
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cookie = 1;
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dwc->chan.cookie = cookie;
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desc->txd.cookie = cookie;
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return cookie;
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}
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/*----------------------------------------------------------------------*/
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/* Called with dwc->lock held and bh disabled */
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static void dwc_dostart(struct dw_dma_chan *dwc, struct dw_desc *first)
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{
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struct dw_dma *dw = to_dw_dma(dwc->chan.device);
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/* ASSERT: channel is idle */
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if (dma_readl(dw, CH_EN) & dwc->mask) {
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dev_err(chan2dev(&dwc->chan),
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"BUG: Attempted to start non-idle channel\n");
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dev_err(chan2dev(&dwc->chan),
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" SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n",
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channel_readl(dwc, SAR),
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channel_readl(dwc, DAR),
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channel_readl(dwc, LLP),
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channel_readl(dwc, CTL_HI),
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channel_readl(dwc, CTL_LO));
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/* The tasklet will hopefully advance the queue... */
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return;
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}
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channel_writel(dwc, LLP, first->txd.phys);
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channel_writel(dwc, CTL_LO,
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DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN);
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channel_writel(dwc, CTL_HI, 0);
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channel_set_bit(dw, CH_EN, dwc->mask);
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}
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/*----------------------------------------------------------------------*/
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static void
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dwc_descriptor_complete(struct dw_dma_chan *dwc, struct dw_desc *desc)
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{
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dma_async_tx_callback callback;
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void *param;
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struct dma_async_tx_descriptor *txd = &desc->txd;
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dev_vdbg(chan2dev(&dwc->chan), "descriptor %u complete\n", txd->cookie);
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dwc->completed = txd->cookie;
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callback = txd->callback;
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param = txd->callback_param;
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dwc_sync_desc_for_cpu(dwc, desc);
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list_splice_init(&txd->tx_list, &dwc->free_list);
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list_move(&desc->desc_node, &dwc->free_list);
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/*
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* We use dma_unmap_page() regardless of how the buffers were
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* mapped before they were submitted...
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*/
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if (!(txd->flags & DMA_COMPL_SKIP_DEST_UNMAP))
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dma_unmap_page(chan2parent(&dwc->chan), desc->lli.dar,
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desc->len, DMA_FROM_DEVICE);
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if (!(txd->flags & DMA_COMPL_SKIP_SRC_UNMAP))
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dma_unmap_page(chan2parent(&dwc->chan), desc->lli.sar,
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desc->len, DMA_TO_DEVICE);
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/*
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* The API requires that no submissions are done from a
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* callback, so we don't need to drop the lock here
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*/
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if (callback)
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callback(param);
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}
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static void dwc_complete_all(struct dw_dma *dw, struct dw_dma_chan *dwc)
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{
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struct dw_desc *desc, *_desc;
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LIST_HEAD(list);
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if (dma_readl(dw, CH_EN) & dwc->mask) {
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dev_err(chan2dev(&dwc->chan),
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"BUG: XFER bit set, but channel not idle!\n");
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/* Try to continue after resetting the channel... */
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channel_clear_bit(dw, CH_EN, dwc->mask);
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while (dma_readl(dw, CH_EN) & dwc->mask)
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cpu_relax();
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}
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/*
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* Submit queued descriptors ASAP, i.e. before we go through
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* the completed ones.
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*/
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if (!list_empty(&dwc->queue))
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dwc_dostart(dwc, dwc_first_queued(dwc));
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list_splice_init(&dwc->active_list, &list);
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list_splice_init(&dwc->queue, &dwc->active_list);
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list_for_each_entry_safe(desc, _desc, &list, desc_node)
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dwc_descriptor_complete(dwc, desc);
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}
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static void dwc_scan_descriptors(struct dw_dma *dw, struct dw_dma_chan *dwc)
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{
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dma_addr_t llp;
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struct dw_desc *desc, *_desc;
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struct dw_desc *child;
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u32 status_xfer;
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/*
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* Clear block interrupt flag before scanning so that we don't
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* miss any, and read LLP before RAW_XFER to ensure it is
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* valid if we decide to scan the list.
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*/
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dma_writel(dw, CLEAR.BLOCK, dwc->mask);
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llp = channel_readl(dwc, LLP);
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status_xfer = dma_readl(dw, RAW.XFER);
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if (status_xfer & dwc->mask) {
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/* Everything we've submitted is done */
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dma_writel(dw, CLEAR.XFER, dwc->mask);
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dwc_complete_all(dw, dwc);
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return;
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}
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dev_vdbg(chan2dev(&dwc->chan), "scan_descriptors: llp=0x%x\n", llp);
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list_for_each_entry_safe(desc, _desc, &dwc->active_list, desc_node) {
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if (desc->lli.llp == llp)
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/* This one is currently in progress */
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return;
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list_for_each_entry(child, &desc->txd.tx_list, desc_node)
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if (child->lli.llp == llp)
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/* Currently in progress */
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return;
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/*
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* No descriptors so far seem to be in progress, i.e.
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* this one must be done.
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*/
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dwc_descriptor_complete(dwc, desc);
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}
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dev_err(chan2dev(&dwc->chan),
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"BUG: All descriptors done, but channel not idle!\n");
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/* Try to continue after resetting the channel... */
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channel_clear_bit(dw, CH_EN, dwc->mask);
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while (dma_readl(dw, CH_EN) & dwc->mask)
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cpu_relax();
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if (!list_empty(&dwc->queue)) {
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dwc_dostart(dwc, dwc_first_queued(dwc));
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list_splice_init(&dwc->queue, &dwc->active_list);
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}
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}
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static void dwc_dump_lli(struct dw_dma_chan *dwc, struct dw_lli *lli)
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{
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dev_printk(KERN_CRIT, chan2dev(&dwc->chan),
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" desc: s0x%x d0x%x l0x%x c0x%x:%x\n",
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lli->sar, lli->dar, lli->llp,
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lli->ctlhi, lli->ctllo);
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}
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static void dwc_handle_error(struct dw_dma *dw, struct dw_dma_chan *dwc)
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{
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struct dw_desc *bad_desc;
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struct dw_desc *child;
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dwc_scan_descriptors(dw, dwc);
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/*
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* The descriptor currently at the head of the active list is
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* borked. Since we don't have any way to report errors, we'll
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* just have to scream loudly and try to carry on.
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*/
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bad_desc = dwc_first_active(dwc);
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list_del_init(&bad_desc->desc_node);
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list_splice_init(&dwc->queue, dwc->active_list.prev);
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/* Clear the error flag and try to restart the controller */
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dma_writel(dw, CLEAR.ERROR, dwc->mask);
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if (!list_empty(&dwc->active_list))
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dwc_dostart(dwc, dwc_first_active(dwc));
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/*
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* KERN_CRITICAL may seem harsh, but since this only happens
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* when someone submits a bad physical address in a
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* descriptor, we should consider ourselves lucky that the
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* controller flagged an error instead of scribbling over
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* random memory locations.
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*/
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dev_printk(KERN_CRIT, chan2dev(&dwc->chan),
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"Bad descriptor submitted for DMA!\n");
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dev_printk(KERN_CRIT, chan2dev(&dwc->chan),
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" cookie: %d\n", bad_desc->txd.cookie);
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dwc_dump_lli(dwc, &bad_desc->lli);
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list_for_each_entry(child, &bad_desc->txd.tx_list, desc_node)
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dwc_dump_lli(dwc, &child->lli);
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/* Pretend the descriptor completed successfully */
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dwc_descriptor_complete(dwc, bad_desc);
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}
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/* --------------------- Cyclic DMA API extensions -------------------- */
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inline dma_addr_t dw_dma_get_src_addr(struct dma_chan *chan)
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{
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struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
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return channel_readl(dwc, SAR);
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}
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EXPORT_SYMBOL(dw_dma_get_src_addr);
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inline dma_addr_t dw_dma_get_dst_addr(struct dma_chan *chan)
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{
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struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
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return channel_readl(dwc, DAR);
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}
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EXPORT_SYMBOL(dw_dma_get_dst_addr);
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/* called with dwc->lock held and all DMAC interrupts disabled */
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static void dwc_handle_cyclic(struct dw_dma *dw, struct dw_dma_chan *dwc,
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u32 status_block, u32 status_err, u32 status_xfer)
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{
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if (status_block & dwc->mask) {
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void (*callback)(void *param);
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void *callback_param;
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dev_vdbg(chan2dev(&dwc->chan), "new cyclic period llp 0x%08x\n",
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channel_readl(dwc, LLP));
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dma_writel(dw, CLEAR.BLOCK, dwc->mask);
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callback = dwc->cdesc->period_callback;
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callback_param = dwc->cdesc->period_callback_param;
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if (callback) {
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spin_unlock(&dwc->lock);
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callback(callback_param);
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spin_lock(&dwc->lock);
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}
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}
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/*
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* Error and transfer complete are highly unlikely, and will most
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* likely be due to a configuration error by the user.
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*/
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if (unlikely(status_err & dwc->mask) ||
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unlikely(status_xfer & dwc->mask)) {
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int i;
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dev_err(chan2dev(&dwc->chan), "cyclic DMA unexpected %s "
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"interrupt, stopping DMA transfer\n",
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status_xfer ? "xfer" : "error");
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dev_err(chan2dev(&dwc->chan),
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" SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n",
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channel_readl(dwc, SAR),
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channel_readl(dwc, DAR),
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channel_readl(dwc, LLP),
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channel_readl(dwc, CTL_HI),
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channel_readl(dwc, CTL_LO));
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channel_clear_bit(dw, CH_EN, dwc->mask);
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while (dma_readl(dw, CH_EN) & dwc->mask)
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cpu_relax();
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/* make sure DMA does not restart by loading a new list */
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channel_writel(dwc, LLP, 0);
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channel_writel(dwc, CTL_LO, 0);
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channel_writel(dwc, CTL_HI, 0);
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dma_writel(dw, CLEAR.BLOCK, dwc->mask);
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dma_writel(dw, CLEAR.ERROR, dwc->mask);
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dma_writel(dw, CLEAR.XFER, dwc->mask);
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for (i = 0; i < dwc->cdesc->periods; i++)
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dwc_dump_lli(dwc, &dwc->cdesc->desc[i]->lli);
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}
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}
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|
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/* ------------------------------------------------------------------------- */
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|
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static void dw_dma_tasklet(unsigned long data)
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{
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struct dw_dma *dw = (struct dw_dma *)data;
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struct dw_dma_chan *dwc;
|
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u32 status_block;
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u32 status_xfer;
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u32 status_err;
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int i;
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status_block = dma_readl(dw, RAW.BLOCK);
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status_xfer = dma_readl(dw, RAW.XFER);
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status_err = dma_readl(dw, RAW.ERROR);
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dev_vdbg(dw->dma.dev, "tasklet: status_block=%x status_err=%x\n",
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status_block, status_err);
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for (i = 0; i < dw->dma.chancnt; i++) {
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dwc = &dw->chan[i];
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spin_lock(&dwc->lock);
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if (test_bit(DW_DMA_IS_CYCLIC, &dwc->flags))
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dwc_handle_cyclic(dw, dwc, status_block, status_err,
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status_xfer);
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else if (status_err & (1 << i))
|
|
dwc_handle_error(dw, dwc);
|
|
else if ((status_block | status_xfer) & (1 << i))
|
|
dwc_scan_descriptors(dw, dwc);
|
|
spin_unlock(&dwc->lock);
|
|
}
|
|
|
|
/*
|
|
* Re-enable interrupts. Block Complete interrupts are only
|
|
* enabled if the INT_EN bit in the descriptor is set. This
|
|
* will trigger a scan before the whole list is done.
|
|
*/
|
|
channel_set_bit(dw, MASK.XFER, dw->all_chan_mask);
|
|
channel_set_bit(dw, MASK.BLOCK, dw->all_chan_mask);
|
|
channel_set_bit(dw, MASK.ERROR, dw->all_chan_mask);
|
|
}
|
|
|
|
static irqreturn_t dw_dma_interrupt(int irq, void *dev_id)
|
|
{
|
|
struct dw_dma *dw = dev_id;
|
|
u32 status;
|
|
|
|
dev_vdbg(dw->dma.dev, "interrupt: status=0x%x\n",
|
|
dma_readl(dw, STATUS_INT));
|
|
|
|
/*
|
|
* Just disable the interrupts. We'll turn them back on in the
|
|
* softirq handler.
|
|
*/
|
|
channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask);
|
|
channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask);
|
|
channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask);
|
|
|
|
status = dma_readl(dw, STATUS_INT);
|
|
if (status) {
|
|
dev_err(dw->dma.dev,
|
|
"BUG: Unexpected interrupts pending: 0x%x\n",
|
|
status);
|
|
|
|
/* Try to recover */
|
|
channel_clear_bit(dw, MASK.XFER, (1 << 8) - 1);
|
|
channel_clear_bit(dw, MASK.BLOCK, (1 << 8) - 1);
|
|
channel_clear_bit(dw, MASK.SRC_TRAN, (1 << 8) - 1);
|
|
channel_clear_bit(dw, MASK.DST_TRAN, (1 << 8) - 1);
|
|
channel_clear_bit(dw, MASK.ERROR, (1 << 8) - 1);
|
|
}
|
|
|
|
tasklet_schedule(&dw->tasklet);
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
/*----------------------------------------------------------------------*/
|
|
|
|
static dma_cookie_t dwc_tx_submit(struct dma_async_tx_descriptor *tx)
|
|
{
|
|
struct dw_desc *desc = txd_to_dw_desc(tx);
|
|
struct dw_dma_chan *dwc = to_dw_dma_chan(tx->chan);
|
|
dma_cookie_t cookie;
|
|
|
|
spin_lock_bh(&dwc->lock);
|
|
cookie = dwc_assign_cookie(dwc, desc);
|
|
|
|
/*
|
|
* REVISIT: We should attempt to chain as many descriptors as
|
|
* possible, perhaps even appending to those already submitted
|
|
* for DMA. But this is hard to do in a race-free manner.
|
|
*/
|
|
if (list_empty(&dwc->active_list)) {
|
|
dev_vdbg(chan2dev(tx->chan), "tx_submit: started %u\n",
|
|
desc->txd.cookie);
|
|
dwc_dostart(dwc, desc);
|
|
list_add_tail(&desc->desc_node, &dwc->active_list);
|
|
} else {
|
|
dev_vdbg(chan2dev(tx->chan), "tx_submit: queued %u\n",
|
|
desc->txd.cookie);
|
|
|
|
list_add_tail(&desc->desc_node, &dwc->queue);
|
|
}
|
|
|
|
spin_unlock_bh(&dwc->lock);
|
|
|
|
return cookie;
|
|
}
|
|
|
|
static struct dma_async_tx_descriptor *
|
|
dwc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
|
|
size_t len, unsigned long flags)
|
|
{
|
|
struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
|
|
struct dw_desc *desc;
|
|
struct dw_desc *first;
|
|
struct dw_desc *prev;
|
|
size_t xfer_count;
|
|
size_t offset;
|
|
unsigned int src_width;
|
|
unsigned int dst_width;
|
|
u32 ctllo;
|
|
|
|
dev_vdbg(chan2dev(chan), "prep_dma_memcpy d0x%x s0x%x l0x%zx f0x%lx\n",
|
|
dest, src, len, flags);
|
|
|
|
if (unlikely(!len)) {
|
|
dev_dbg(chan2dev(chan), "prep_dma_memcpy: length is zero!\n");
|
|
return NULL;
|
|
}
|
|
|
|
/*
|
|
* We can be a lot more clever here, but this should take care
|
|
* of the most common optimization.
|
|
*/
|
|
if (!((src | dest | len) & 3))
|
|
src_width = dst_width = 2;
|
|
else if (!((src | dest | len) & 1))
|
|
src_width = dst_width = 1;
|
|
else
|
|
src_width = dst_width = 0;
|
|
|
|
ctllo = DWC_DEFAULT_CTLLO
|
|
| DWC_CTLL_DST_WIDTH(dst_width)
|
|
| DWC_CTLL_SRC_WIDTH(src_width)
|
|
| DWC_CTLL_DST_INC
|
|
| DWC_CTLL_SRC_INC
|
|
| DWC_CTLL_FC_M2M;
|
|
prev = first = NULL;
|
|
|
|
for (offset = 0; offset < len; offset += xfer_count << src_width) {
|
|
xfer_count = min_t(size_t, (len - offset) >> src_width,
|
|
DWC_MAX_COUNT);
|
|
|
|
desc = dwc_desc_get(dwc);
|
|
if (!desc)
|
|
goto err_desc_get;
|
|
|
|
desc->lli.sar = src + offset;
|
|
desc->lli.dar = dest + offset;
|
|
desc->lli.ctllo = ctllo;
|
|
desc->lli.ctlhi = xfer_count;
|
|
|
|
if (!first) {
|
|
first = desc;
|
|
} else {
|
|
prev->lli.llp = desc->txd.phys;
|
|
dma_sync_single_for_device(chan2parent(chan),
|
|
prev->txd.phys, sizeof(prev->lli),
|
|
DMA_TO_DEVICE);
|
|
list_add_tail(&desc->desc_node,
|
|
&first->txd.tx_list);
|
|
}
|
|
prev = desc;
|
|
}
|
|
|
|
|
|
if (flags & DMA_PREP_INTERRUPT)
|
|
/* Trigger interrupt after last block */
|
|
prev->lli.ctllo |= DWC_CTLL_INT_EN;
|
|
|
|
prev->lli.llp = 0;
|
|
dma_sync_single_for_device(chan2parent(chan),
|
|
prev->txd.phys, sizeof(prev->lli),
|
|
DMA_TO_DEVICE);
|
|
|
|
first->txd.flags = flags;
|
|
first->len = len;
|
|
|
|
return &first->txd;
|
|
|
|
err_desc_get:
|
|
dwc_desc_put(dwc, first);
|
|
return NULL;
|
|
}
|
|
|
|
static struct dma_async_tx_descriptor *
|
|
dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
|
|
unsigned int sg_len, enum dma_data_direction direction,
|
|
unsigned long flags)
|
|
{
|
|
struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
|
|
struct dw_dma_slave *dws = chan->private;
|
|
struct dw_desc *prev;
|
|
struct dw_desc *first;
|
|
u32 ctllo;
|
|
dma_addr_t reg;
|
|
unsigned int reg_width;
|
|
unsigned int mem_width;
|
|
unsigned int i;
|
|
struct scatterlist *sg;
|
|
size_t total_len = 0;
|
|
|
|
dev_vdbg(chan2dev(chan), "prep_dma_slave\n");
|
|
|
|
if (unlikely(!dws || !sg_len))
|
|
return NULL;
|
|
|
|
reg_width = dws->reg_width;
|
|
prev = first = NULL;
|
|
|
|
sg_len = dma_map_sg(chan2parent(chan), sgl, sg_len, direction);
|
|
|
|
switch (direction) {
|
|
case DMA_TO_DEVICE:
|
|
ctllo = (DWC_DEFAULT_CTLLO
|
|
| DWC_CTLL_DST_WIDTH(reg_width)
|
|
| DWC_CTLL_DST_FIX
|
|
| DWC_CTLL_SRC_INC
|
|
| DWC_CTLL_FC_M2P);
|
|
reg = dws->tx_reg;
|
|
for_each_sg(sgl, sg, sg_len, i) {
|
|
struct dw_desc *desc;
|
|
u32 len;
|
|
u32 mem;
|
|
|
|
desc = dwc_desc_get(dwc);
|
|
if (!desc) {
|
|
dev_err(chan2dev(chan),
|
|
"not enough descriptors available\n");
|
|
goto err_desc_get;
|
|
}
|
|
|
|
mem = sg_phys(sg);
|
|
len = sg_dma_len(sg);
|
|
mem_width = 2;
|
|
if (unlikely(mem & 3 || len & 3))
|
|
mem_width = 0;
|
|
|
|
desc->lli.sar = mem;
|
|
desc->lli.dar = reg;
|
|
desc->lli.ctllo = ctllo | DWC_CTLL_SRC_WIDTH(mem_width);
|
|
desc->lli.ctlhi = len >> mem_width;
|
|
|
|
if (!first) {
|
|
first = desc;
|
|
} else {
|
|
prev->lli.llp = desc->txd.phys;
|
|
dma_sync_single_for_device(chan2parent(chan),
|
|
prev->txd.phys,
|
|
sizeof(prev->lli),
|
|
DMA_TO_DEVICE);
|
|
list_add_tail(&desc->desc_node,
|
|
&first->txd.tx_list);
|
|
}
|
|
prev = desc;
|
|
total_len += len;
|
|
}
|
|
break;
|
|
case DMA_FROM_DEVICE:
|
|
ctllo = (DWC_DEFAULT_CTLLO
|
|
| DWC_CTLL_SRC_WIDTH(reg_width)
|
|
| DWC_CTLL_DST_INC
|
|
| DWC_CTLL_SRC_FIX
|
|
| DWC_CTLL_FC_P2M);
|
|
|
|
reg = dws->rx_reg;
|
|
for_each_sg(sgl, sg, sg_len, i) {
|
|
struct dw_desc *desc;
|
|
u32 len;
|
|
u32 mem;
|
|
|
|
desc = dwc_desc_get(dwc);
|
|
if (!desc) {
|
|
dev_err(chan2dev(chan),
|
|
"not enough descriptors available\n");
|
|
goto err_desc_get;
|
|
}
|
|
|
|
mem = sg_phys(sg);
|
|
len = sg_dma_len(sg);
|
|
mem_width = 2;
|
|
if (unlikely(mem & 3 || len & 3))
|
|
mem_width = 0;
|
|
|
|
desc->lli.sar = reg;
|
|
desc->lli.dar = mem;
|
|
desc->lli.ctllo = ctllo | DWC_CTLL_DST_WIDTH(mem_width);
|
|
desc->lli.ctlhi = len >> reg_width;
|
|
|
|
if (!first) {
|
|
first = desc;
|
|
} else {
|
|
prev->lli.llp = desc->txd.phys;
|
|
dma_sync_single_for_device(chan2parent(chan),
|
|
prev->txd.phys,
|
|
sizeof(prev->lli),
|
|
DMA_TO_DEVICE);
|
|
list_add_tail(&desc->desc_node,
|
|
&first->txd.tx_list);
|
|
}
|
|
prev = desc;
|
|
total_len += len;
|
|
}
|
|
break;
|
|
default:
|
|
return NULL;
|
|
}
|
|
|
|
if (flags & DMA_PREP_INTERRUPT)
|
|
/* Trigger interrupt after last block */
|
|
prev->lli.ctllo |= DWC_CTLL_INT_EN;
|
|
|
|
prev->lli.llp = 0;
|
|
dma_sync_single_for_device(chan2parent(chan),
|
|
prev->txd.phys, sizeof(prev->lli),
|
|
DMA_TO_DEVICE);
|
|
|
|
first->len = total_len;
|
|
|
|
return &first->txd;
|
|
|
|
err_desc_get:
|
|
dwc_desc_put(dwc, first);
|
|
return NULL;
|
|
}
|
|
|
|
static void dwc_terminate_all(struct dma_chan *chan)
|
|
{
|
|
struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
|
|
struct dw_dma *dw = to_dw_dma(chan->device);
|
|
struct dw_desc *desc, *_desc;
|
|
LIST_HEAD(list);
|
|
|
|
/*
|
|
* This is only called when something went wrong elsewhere, so
|
|
* we don't really care about the data. Just disable the
|
|
* channel. We still have to poll the channel enable bit due
|
|
* to AHB/HSB limitations.
|
|
*/
|
|
spin_lock_bh(&dwc->lock);
|
|
|
|
channel_clear_bit(dw, CH_EN, dwc->mask);
|
|
|
|
while (dma_readl(dw, CH_EN) & dwc->mask)
|
|
cpu_relax();
|
|
|
|
/* active_list entries will end up before queued entries */
|
|
list_splice_init(&dwc->queue, &list);
|
|
list_splice_init(&dwc->active_list, &list);
|
|
|
|
spin_unlock_bh(&dwc->lock);
|
|
|
|
/* Flush all pending and queued descriptors */
|
|
list_for_each_entry_safe(desc, _desc, &list, desc_node)
|
|
dwc_descriptor_complete(dwc, desc);
|
|
}
|
|
|
|
static enum dma_status
|
|
dwc_is_tx_complete(struct dma_chan *chan,
|
|
dma_cookie_t cookie,
|
|
dma_cookie_t *done, dma_cookie_t *used)
|
|
{
|
|
struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
|
|
dma_cookie_t last_used;
|
|
dma_cookie_t last_complete;
|
|
int ret;
|
|
|
|
last_complete = dwc->completed;
|
|
last_used = chan->cookie;
|
|
|
|
ret = dma_async_is_complete(cookie, last_complete, last_used);
|
|
if (ret != DMA_SUCCESS) {
|
|
dwc_scan_descriptors(to_dw_dma(chan->device), dwc);
|
|
|
|
last_complete = dwc->completed;
|
|
last_used = chan->cookie;
|
|
|
|
ret = dma_async_is_complete(cookie, last_complete, last_used);
|
|
}
|
|
|
|
if (done)
|
|
*done = last_complete;
|
|
if (used)
|
|
*used = last_used;
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void dwc_issue_pending(struct dma_chan *chan)
|
|
{
|
|
struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
|
|
|
|
spin_lock_bh(&dwc->lock);
|
|
if (!list_empty(&dwc->queue))
|
|
dwc_scan_descriptors(to_dw_dma(chan->device), dwc);
|
|
spin_unlock_bh(&dwc->lock);
|
|
}
|
|
|
|
static int dwc_alloc_chan_resources(struct dma_chan *chan)
|
|
{
|
|
struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
|
|
struct dw_dma *dw = to_dw_dma(chan->device);
|
|
struct dw_desc *desc;
|
|
struct dw_dma_slave *dws;
|
|
int i;
|
|
u32 cfghi;
|
|
u32 cfglo;
|
|
|
|
dev_vdbg(chan2dev(chan), "alloc_chan_resources\n");
|
|
|
|
/* ASSERT: channel is idle */
|
|
if (dma_readl(dw, CH_EN) & dwc->mask) {
|
|
dev_dbg(chan2dev(chan), "DMA channel not idle?\n");
|
|
return -EIO;
|
|
}
|
|
|
|
dwc->completed = chan->cookie = 1;
|
|
|
|
cfghi = DWC_CFGH_FIFO_MODE;
|
|
cfglo = 0;
|
|
|
|
dws = chan->private;
|
|
if (dws) {
|
|
/*
|
|
* We need controller-specific data to set up slave
|
|
* transfers.
|
|
*/
|
|
BUG_ON(!dws->dma_dev || dws->dma_dev != dw->dma.dev);
|
|
|
|
cfghi = dws->cfg_hi;
|
|
cfglo = dws->cfg_lo;
|
|
}
|
|
channel_writel(dwc, CFG_LO, cfglo);
|
|
channel_writel(dwc, CFG_HI, cfghi);
|
|
|
|
/*
|
|
* NOTE: some controllers may have additional features that we
|
|
* need to initialize here, like "scatter-gather" (which
|
|
* doesn't mean what you think it means), and status writeback.
|
|
*/
|
|
|
|
spin_lock_bh(&dwc->lock);
|
|
i = dwc->descs_allocated;
|
|
while (dwc->descs_allocated < NR_DESCS_PER_CHANNEL) {
|
|
spin_unlock_bh(&dwc->lock);
|
|
|
|
desc = kzalloc(sizeof(struct dw_desc), GFP_KERNEL);
|
|
if (!desc) {
|
|
dev_info(chan2dev(chan),
|
|
"only allocated %d descriptors\n", i);
|
|
spin_lock_bh(&dwc->lock);
|
|
break;
|
|
}
|
|
|
|
dma_async_tx_descriptor_init(&desc->txd, chan);
|
|
desc->txd.tx_submit = dwc_tx_submit;
|
|
desc->txd.flags = DMA_CTRL_ACK;
|
|
desc->txd.phys = dma_map_single(chan2parent(chan), &desc->lli,
|
|
sizeof(desc->lli), DMA_TO_DEVICE);
|
|
dwc_desc_put(dwc, desc);
|
|
|
|
spin_lock_bh(&dwc->lock);
|
|
i = ++dwc->descs_allocated;
|
|
}
|
|
|
|
/* Enable interrupts */
|
|
channel_set_bit(dw, MASK.XFER, dwc->mask);
|
|
channel_set_bit(dw, MASK.BLOCK, dwc->mask);
|
|
channel_set_bit(dw, MASK.ERROR, dwc->mask);
|
|
|
|
spin_unlock_bh(&dwc->lock);
|
|
|
|
dev_dbg(chan2dev(chan),
|
|
"alloc_chan_resources allocated %d descriptors\n", i);
|
|
|
|
return i;
|
|
}
|
|
|
|
static void dwc_free_chan_resources(struct dma_chan *chan)
|
|
{
|
|
struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
|
|
struct dw_dma *dw = to_dw_dma(chan->device);
|
|
struct dw_desc *desc, *_desc;
|
|
LIST_HEAD(list);
|
|
|
|
dev_dbg(chan2dev(chan), "free_chan_resources (descs allocated=%u)\n",
|
|
dwc->descs_allocated);
|
|
|
|
/* ASSERT: channel is idle */
|
|
BUG_ON(!list_empty(&dwc->active_list));
|
|
BUG_ON(!list_empty(&dwc->queue));
|
|
BUG_ON(dma_readl(to_dw_dma(chan->device), CH_EN) & dwc->mask);
|
|
|
|
spin_lock_bh(&dwc->lock);
|
|
list_splice_init(&dwc->free_list, &list);
|
|
dwc->descs_allocated = 0;
|
|
|
|
/* Disable interrupts */
|
|
channel_clear_bit(dw, MASK.XFER, dwc->mask);
|
|
channel_clear_bit(dw, MASK.BLOCK, dwc->mask);
|
|
channel_clear_bit(dw, MASK.ERROR, dwc->mask);
|
|
|
|
spin_unlock_bh(&dwc->lock);
|
|
|
|
list_for_each_entry_safe(desc, _desc, &list, desc_node) {
|
|
dev_vdbg(chan2dev(chan), " freeing descriptor %p\n", desc);
|
|
dma_unmap_single(chan2parent(chan), desc->txd.phys,
|
|
sizeof(desc->lli), DMA_TO_DEVICE);
|
|
kfree(desc);
|
|
}
|
|
|
|
dev_vdbg(chan2dev(chan), "free_chan_resources done\n");
|
|
}
|
|
|
|
/* --------------------- Cyclic DMA API extensions -------------------- */
|
|
|
|
/**
|
|
* dw_dma_cyclic_start - start the cyclic DMA transfer
|
|
* @chan: the DMA channel to start
|
|
*
|
|
* Must be called with soft interrupts disabled. Returns zero on success or
|
|
* -errno on failure.
|
|
*/
|
|
int dw_dma_cyclic_start(struct dma_chan *chan)
|
|
{
|
|
struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
|
|
struct dw_dma *dw = to_dw_dma(dwc->chan.device);
|
|
|
|
if (!test_bit(DW_DMA_IS_CYCLIC, &dwc->flags)) {
|
|
dev_err(chan2dev(&dwc->chan), "missing prep for cyclic DMA\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
spin_lock(&dwc->lock);
|
|
|
|
/* assert channel is idle */
|
|
if (dma_readl(dw, CH_EN) & dwc->mask) {
|
|
dev_err(chan2dev(&dwc->chan),
|
|
"BUG: Attempted to start non-idle channel\n");
|
|
dev_err(chan2dev(&dwc->chan),
|
|
" SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n",
|
|
channel_readl(dwc, SAR),
|
|
channel_readl(dwc, DAR),
|
|
channel_readl(dwc, LLP),
|
|
channel_readl(dwc, CTL_HI),
|
|
channel_readl(dwc, CTL_LO));
|
|
spin_unlock(&dwc->lock);
|
|
return -EBUSY;
|
|
}
|
|
|
|
dma_writel(dw, CLEAR.BLOCK, dwc->mask);
|
|
dma_writel(dw, CLEAR.ERROR, dwc->mask);
|
|
dma_writel(dw, CLEAR.XFER, dwc->mask);
|
|
|
|
/* setup DMAC channel registers */
|
|
channel_writel(dwc, LLP, dwc->cdesc->desc[0]->txd.phys);
|
|
channel_writel(dwc, CTL_LO, DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN);
|
|
channel_writel(dwc, CTL_HI, 0);
|
|
|
|
channel_set_bit(dw, CH_EN, dwc->mask);
|
|
|
|
spin_unlock(&dwc->lock);
|
|
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL(dw_dma_cyclic_start);
|
|
|
|
/**
|
|
* dw_dma_cyclic_stop - stop the cyclic DMA transfer
|
|
* @chan: the DMA channel to stop
|
|
*
|
|
* Must be called with soft interrupts disabled.
|
|
*/
|
|
void dw_dma_cyclic_stop(struct dma_chan *chan)
|
|
{
|
|
struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
|
|
struct dw_dma *dw = to_dw_dma(dwc->chan.device);
|
|
|
|
spin_lock(&dwc->lock);
|
|
|
|
channel_clear_bit(dw, CH_EN, dwc->mask);
|
|
while (dma_readl(dw, CH_EN) & dwc->mask)
|
|
cpu_relax();
|
|
|
|
spin_unlock(&dwc->lock);
|
|
}
|
|
EXPORT_SYMBOL(dw_dma_cyclic_stop);
|
|
|
|
/**
|
|
* dw_dma_cyclic_prep - prepare the cyclic DMA transfer
|
|
* @chan: the DMA channel to prepare
|
|
* @buf_addr: physical DMA address where the buffer starts
|
|
* @buf_len: total number of bytes for the entire buffer
|
|
* @period_len: number of bytes for each period
|
|
* @direction: transfer direction, to or from device
|
|
*
|
|
* Must be called before trying to start the transfer. Returns a valid struct
|
|
* dw_cyclic_desc if successful or an ERR_PTR(-errno) if not successful.
|
|
*/
|
|
struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan,
|
|
dma_addr_t buf_addr, size_t buf_len, size_t period_len,
|
|
enum dma_data_direction direction)
|
|
{
|
|
struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
|
|
struct dw_cyclic_desc *cdesc;
|
|
struct dw_cyclic_desc *retval = NULL;
|
|
struct dw_desc *desc;
|
|
struct dw_desc *last = NULL;
|
|
struct dw_dma_slave *dws = chan->private;
|
|
unsigned long was_cyclic;
|
|
unsigned int reg_width;
|
|
unsigned int periods;
|
|
unsigned int i;
|
|
|
|
spin_lock_bh(&dwc->lock);
|
|
if (!list_empty(&dwc->queue) || !list_empty(&dwc->active_list)) {
|
|
spin_unlock_bh(&dwc->lock);
|
|
dev_dbg(chan2dev(&dwc->chan),
|
|
"queue and/or active list are not empty\n");
|
|
return ERR_PTR(-EBUSY);
|
|
}
|
|
|
|
was_cyclic = test_and_set_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
|
|
spin_unlock_bh(&dwc->lock);
|
|
if (was_cyclic) {
|
|
dev_dbg(chan2dev(&dwc->chan),
|
|
"channel already prepared for cyclic DMA\n");
|
|
return ERR_PTR(-EBUSY);
|
|
}
|
|
|
|
retval = ERR_PTR(-EINVAL);
|
|
reg_width = dws->reg_width;
|
|
periods = buf_len / period_len;
|
|
|
|
/* Check for too big/unaligned periods and unaligned DMA buffer. */
|
|
if (period_len > (DWC_MAX_COUNT << reg_width))
|
|
goto out_err;
|
|
if (unlikely(period_len & ((1 << reg_width) - 1)))
|
|
goto out_err;
|
|
if (unlikely(buf_addr & ((1 << reg_width) - 1)))
|
|
goto out_err;
|
|
if (unlikely(!(direction & (DMA_TO_DEVICE | DMA_FROM_DEVICE))))
|
|
goto out_err;
|
|
|
|
retval = ERR_PTR(-ENOMEM);
|
|
|
|
if (periods > NR_DESCS_PER_CHANNEL)
|
|
goto out_err;
|
|
|
|
cdesc = kzalloc(sizeof(struct dw_cyclic_desc), GFP_KERNEL);
|
|
if (!cdesc)
|
|
goto out_err;
|
|
|
|
cdesc->desc = kzalloc(sizeof(struct dw_desc *) * periods, GFP_KERNEL);
|
|
if (!cdesc->desc)
|
|
goto out_err_alloc;
|
|
|
|
for (i = 0; i < periods; i++) {
|
|
desc = dwc_desc_get(dwc);
|
|
if (!desc)
|
|
goto out_err_desc_get;
|
|
|
|
switch (direction) {
|
|
case DMA_TO_DEVICE:
|
|
desc->lli.dar = dws->tx_reg;
|
|
desc->lli.sar = buf_addr + (period_len * i);
|
|
desc->lli.ctllo = (DWC_DEFAULT_CTLLO
|
|
| DWC_CTLL_DST_WIDTH(reg_width)
|
|
| DWC_CTLL_SRC_WIDTH(reg_width)
|
|
| DWC_CTLL_DST_FIX
|
|
| DWC_CTLL_SRC_INC
|
|
| DWC_CTLL_FC_M2P
|
|
| DWC_CTLL_INT_EN);
|
|
break;
|
|
case DMA_FROM_DEVICE:
|
|
desc->lli.dar = buf_addr + (period_len * i);
|
|
desc->lli.sar = dws->rx_reg;
|
|
desc->lli.ctllo = (DWC_DEFAULT_CTLLO
|
|
| DWC_CTLL_SRC_WIDTH(reg_width)
|
|
| DWC_CTLL_DST_WIDTH(reg_width)
|
|
| DWC_CTLL_DST_INC
|
|
| DWC_CTLL_SRC_FIX
|
|
| DWC_CTLL_FC_P2M
|
|
| DWC_CTLL_INT_EN);
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
desc->lli.ctlhi = (period_len >> reg_width);
|
|
cdesc->desc[i] = desc;
|
|
|
|
if (last) {
|
|
last->lli.llp = desc->txd.phys;
|
|
dma_sync_single_for_device(chan2parent(chan),
|
|
last->txd.phys, sizeof(last->lli),
|
|
DMA_TO_DEVICE);
|
|
}
|
|
|
|
last = desc;
|
|
}
|
|
|
|
/* lets make a cyclic list */
|
|
last->lli.llp = cdesc->desc[0]->txd.phys;
|
|
dma_sync_single_for_device(chan2parent(chan), last->txd.phys,
|
|
sizeof(last->lli), DMA_TO_DEVICE);
|
|
|
|
dev_dbg(chan2dev(&dwc->chan), "cyclic prepared buf 0x%08x len %zu "
|
|
"period %zu periods %d\n", buf_addr, buf_len,
|
|
period_len, periods);
|
|
|
|
cdesc->periods = periods;
|
|
dwc->cdesc = cdesc;
|
|
|
|
return cdesc;
|
|
|
|
out_err_desc_get:
|
|
while (i--)
|
|
dwc_desc_put(dwc, cdesc->desc[i]);
|
|
out_err_alloc:
|
|
kfree(cdesc);
|
|
out_err:
|
|
clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
|
|
return (struct dw_cyclic_desc *)retval;
|
|
}
|
|
EXPORT_SYMBOL(dw_dma_cyclic_prep);
|
|
|
|
/**
|
|
* dw_dma_cyclic_free - free a prepared cyclic DMA transfer
|
|
* @chan: the DMA channel to free
|
|
*/
|
|
void dw_dma_cyclic_free(struct dma_chan *chan)
|
|
{
|
|
struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
|
|
struct dw_dma *dw = to_dw_dma(dwc->chan.device);
|
|
struct dw_cyclic_desc *cdesc = dwc->cdesc;
|
|
int i;
|
|
|
|
dev_dbg(chan2dev(&dwc->chan), "cyclic free\n");
|
|
|
|
if (!cdesc)
|
|
return;
|
|
|
|
spin_lock_bh(&dwc->lock);
|
|
|
|
channel_clear_bit(dw, CH_EN, dwc->mask);
|
|
while (dma_readl(dw, CH_EN) & dwc->mask)
|
|
cpu_relax();
|
|
|
|
dma_writel(dw, CLEAR.BLOCK, dwc->mask);
|
|
dma_writel(dw, CLEAR.ERROR, dwc->mask);
|
|
dma_writel(dw, CLEAR.XFER, dwc->mask);
|
|
|
|
spin_unlock_bh(&dwc->lock);
|
|
|
|
for (i = 0; i < cdesc->periods; i++)
|
|
dwc_desc_put(dwc, cdesc->desc[i]);
|
|
|
|
kfree(cdesc->desc);
|
|
kfree(cdesc);
|
|
|
|
clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
|
|
}
|
|
EXPORT_SYMBOL(dw_dma_cyclic_free);
|
|
|
|
/*----------------------------------------------------------------------*/
|
|
|
|
static void dw_dma_off(struct dw_dma *dw)
|
|
{
|
|
dma_writel(dw, CFG, 0);
|
|
|
|
channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask);
|
|
channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask);
|
|
channel_clear_bit(dw, MASK.SRC_TRAN, dw->all_chan_mask);
|
|
channel_clear_bit(dw, MASK.DST_TRAN, dw->all_chan_mask);
|
|
channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask);
|
|
|
|
while (dma_readl(dw, CFG) & DW_CFG_DMA_EN)
|
|
cpu_relax();
|
|
}
|
|
|
|
static int __init dw_probe(struct platform_device *pdev)
|
|
{
|
|
struct dw_dma_platform_data *pdata;
|
|
struct resource *io;
|
|
struct dw_dma *dw;
|
|
size_t size;
|
|
int irq;
|
|
int err;
|
|
int i;
|
|
|
|
pdata = pdev->dev.platform_data;
|
|
if (!pdata || pdata->nr_channels > DW_DMA_MAX_NR_CHANNELS)
|
|
return -EINVAL;
|
|
|
|
io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
if (!io)
|
|
return -EINVAL;
|
|
|
|
irq = platform_get_irq(pdev, 0);
|
|
if (irq < 0)
|
|
return irq;
|
|
|
|
size = sizeof(struct dw_dma);
|
|
size += pdata->nr_channels * sizeof(struct dw_dma_chan);
|
|
dw = kzalloc(size, GFP_KERNEL);
|
|
if (!dw)
|
|
return -ENOMEM;
|
|
|
|
if (!request_mem_region(io->start, DW_REGLEN, pdev->dev.driver->name)) {
|
|
err = -EBUSY;
|
|
goto err_kfree;
|
|
}
|
|
|
|
memset(dw, 0, sizeof *dw);
|
|
|
|
dw->regs = ioremap(io->start, DW_REGLEN);
|
|
if (!dw->regs) {
|
|
err = -ENOMEM;
|
|
goto err_release_r;
|
|
}
|
|
|
|
dw->clk = clk_get(&pdev->dev, "hclk");
|
|
if (IS_ERR(dw->clk)) {
|
|
err = PTR_ERR(dw->clk);
|
|
goto err_clk;
|
|
}
|
|
clk_enable(dw->clk);
|
|
|
|
/* force dma off, just in case */
|
|
dw_dma_off(dw);
|
|
|
|
err = request_irq(irq, dw_dma_interrupt, 0, "dw_dmac", dw);
|
|
if (err)
|
|
goto err_irq;
|
|
|
|
platform_set_drvdata(pdev, dw);
|
|
|
|
tasklet_init(&dw->tasklet, dw_dma_tasklet, (unsigned long)dw);
|
|
|
|
dw->all_chan_mask = (1 << pdata->nr_channels) - 1;
|
|
|
|
INIT_LIST_HEAD(&dw->dma.channels);
|
|
for (i = 0; i < pdata->nr_channels; i++, dw->dma.chancnt++) {
|
|
struct dw_dma_chan *dwc = &dw->chan[i];
|
|
|
|
dwc->chan.device = &dw->dma;
|
|
dwc->chan.cookie = dwc->completed = 1;
|
|
dwc->chan.chan_id = i;
|
|
list_add_tail(&dwc->chan.device_node, &dw->dma.channels);
|
|
|
|
dwc->ch_regs = &__dw_regs(dw)->CHAN[i];
|
|
spin_lock_init(&dwc->lock);
|
|
dwc->mask = 1 << i;
|
|
|
|
INIT_LIST_HEAD(&dwc->active_list);
|
|
INIT_LIST_HEAD(&dwc->queue);
|
|
INIT_LIST_HEAD(&dwc->free_list);
|
|
|
|
channel_clear_bit(dw, CH_EN, dwc->mask);
|
|
}
|
|
|
|
/* Clear/disable all interrupts on all channels. */
|
|
dma_writel(dw, CLEAR.XFER, dw->all_chan_mask);
|
|
dma_writel(dw, CLEAR.BLOCK, dw->all_chan_mask);
|
|
dma_writel(dw, CLEAR.SRC_TRAN, dw->all_chan_mask);
|
|
dma_writel(dw, CLEAR.DST_TRAN, dw->all_chan_mask);
|
|
dma_writel(dw, CLEAR.ERROR, dw->all_chan_mask);
|
|
|
|
channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask);
|
|
channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask);
|
|
channel_clear_bit(dw, MASK.SRC_TRAN, dw->all_chan_mask);
|
|
channel_clear_bit(dw, MASK.DST_TRAN, dw->all_chan_mask);
|
|
channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask);
|
|
|
|
dma_cap_set(DMA_MEMCPY, dw->dma.cap_mask);
|
|
dma_cap_set(DMA_SLAVE, dw->dma.cap_mask);
|
|
dw->dma.dev = &pdev->dev;
|
|
dw->dma.device_alloc_chan_resources = dwc_alloc_chan_resources;
|
|
dw->dma.device_free_chan_resources = dwc_free_chan_resources;
|
|
|
|
dw->dma.device_prep_dma_memcpy = dwc_prep_dma_memcpy;
|
|
|
|
dw->dma.device_prep_slave_sg = dwc_prep_slave_sg;
|
|
dw->dma.device_terminate_all = dwc_terminate_all;
|
|
|
|
dw->dma.device_is_tx_complete = dwc_is_tx_complete;
|
|
dw->dma.device_issue_pending = dwc_issue_pending;
|
|
|
|
dma_writel(dw, CFG, DW_CFG_DMA_EN);
|
|
|
|
printk(KERN_INFO "%s: DesignWare DMA Controller, %d channels\n",
|
|
pdev->dev.bus_id, dw->dma.chancnt);
|
|
|
|
dma_async_device_register(&dw->dma);
|
|
|
|
return 0;
|
|
|
|
err_irq:
|
|
clk_disable(dw->clk);
|
|
clk_put(dw->clk);
|
|
err_clk:
|
|
iounmap(dw->regs);
|
|
dw->regs = NULL;
|
|
err_release_r:
|
|
release_resource(io);
|
|
err_kfree:
|
|
kfree(dw);
|
|
return err;
|
|
}
|
|
|
|
static int __exit dw_remove(struct platform_device *pdev)
|
|
{
|
|
struct dw_dma *dw = platform_get_drvdata(pdev);
|
|
struct dw_dma_chan *dwc, *_dwc;
|
|
struct resource *io;
|
|
|
|
dw_dma_off(dw);
|
|
dma_async_device_unregister(&dw->dma);
|
|
|
|
free_irq(platform_get_irq(pdev, 0), dw);
|
|
tasklet_kill(&dw->tasklet);
|
|
|
|
list_for_each_entry_safe(dwc, _dwc, &dw->dma.channels,
|
|
chan.device_node) {
|
|
list_del(&dwc->chan.device_node);
|
|
channel_clear_bit(dw, CH_EN, dwc->mask);
|
|
}
|
|
|
|
clk_disable(dw->clk);
|
|
clk_put(dw->clk);
|
|
|
|
iounmap(dw->regs);
|
|
dw->regs = NULL;
|
|
|
|
io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
release_mem_region(io->start, DW_REGLEN);
|
|
|
|
kfree(dw);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void dw_shutdown(struct platform_device *pdev)
|
|
{
|
|
struct dw_dma *dw = platform_get_drvdata(pdev);
|
|
|
|
dw_dma_off(platform_get_drvdata(pdev));
|
|
clk_disable(dw->clk);
|
|
}
|
|
|
|
static int dw_suspend_late(struct platform_device *pdev, pm_message_t mesg)
|
|
{
|
|
struct dw_dma *dw = platform_get_drvdata(pdev);
|
|
|
|
dw_dma_off(platform_get_drvdata(pdev));
|
|
clk_disable(dw->clk);
|
|
return 0;
|
|
}
|
|
|
|
static int dw_resume_early(struct platform_device *pdev)
|
|
{
|
|
struct dw_dma *dw = platform_get_drvdata(pdev);
|
|
|
|
clk_enable(dw->clk);
|
|
dma_writel(dw, CFG, DW_CFG_DMA_EN);
|
|
return 0;
|
|
|
|
}
|
|
|
|
static struct platform_driver dw_driver = {
|
|
.remove = __exit_p(dw_remove),
|
|
.shutdown = dw_shutdown,
|
|
.suspend_late = dw_suspend_late,
|
|
.resume_early = dw_resume_early,
|
|
.driver = {
|
|
.name = "dw_dmac",
|
|
},
|
|
};
|
|
|
|
static int __init dw_init(void)
|
|
{
|
|
return platform_driver_probe(&dw_driver, dw_probe);
|
|
}
|
|
module_init(dw_init);
|
|
|
|
static void __exit dw_exit(void)
|
|
{
|
|
platform_driver_unregister(&dw_driver);
|
|
}
|
|
module_exit(dw_exit);
|
|
|
|
MODULE_LICENSE("GPL v2");
|
|
MODULE_DESCRIPTION("Synopsys DesignWare DMA Controller driver");
|
|
MODULE_AUTHOR("Haavard Skinnemoen <haavard.skinnemoen@atmel.com>");
|