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Sometimes we don't know memory store operations happen on exactly which memory (or cache) level, the memory level flag is set to PERF_MEM_LVL_NA in this case; a practical example is Arm SPE AUX trace sets this flag for all store operations due to absent info for cache level. This patch is to add a new item "st_na" in structure c2c_stats to add statistics for store operations with no available cache level. Signed-off-by: Leo Yan <leo.yan@linaro.org> Acked-by: Jiri Olsa <jolsa@kernel.org> Cc: Adam Li <adamli@amperemail.onmicrosoft.com> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Ali Saidi <alisaidi@amazon.com> Cc: Alyssa Ross <hi@alyssa.is> Cc: German Gomez <german.gomez@arm.com> Cc: Ian Rogers <irogers@google.com> Cc: Ingo Molnar <mingo@redhat.com> Cc: James Clark <james.clark@arm.com> Cc: Joe Mario <jmario@redhat.com> Cc: Kajol Jain <kjain@linux.ibm.com> Cc: Kan Liang <kan.liang@linux.intel.com> Cc: Li Huafei <lihuafei1@huawei.com> Cc: Like Xu <likexu@tencent.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Peter Zijlstra <peterz@infradead.org> Link: https://lore.kernel.org/r/20220518055729.1869566-2-leo.yan@linaro.org Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
95 lines
3.5 KiB
C
95 lines
3.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __PERF_MEM_EVENTS_H
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#define __PERF_MEM_EVENTS_H
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#include <stdbool.h>
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#include <stdint.h>
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#include <stdio.h>
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#include <linux/types.h>
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#include <linux/refcount.h>
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#include <linux/perf_event.h>
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#include "stat.h"
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#include "evsel.h"
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struct perf_mem_event {
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bool record;
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bool supported;
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const char *tag;
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const char *name;
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const char *sysfs_name;
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};
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struct mem_info {
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struct addr_map_symbol iaddr;
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struct addr_map_symbol daddr;
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union perf_mem_data_src data_src;
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refcount_t refcnt;
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};
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enum {
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PERF_MEM_EVENTS__LOAD,
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PERF_MEM_EVENTS__STORE,
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PERF_MEM_EVENTS__LOAD_STORE,
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PERF_MEM_EVENTS__MAX,
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};
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extern unsigned int perf_mem_events__loads_ldlat;
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int perf_mem_events__parse(const char *str);
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int perf_mem_events__init(void);
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char *perf_mem_events__name(int i, char *pmu_name);
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struct perf_mem_event *perf_mem_events__ptr(int i);
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bool is_mem_loads_aux_event(struct evsel *leader);
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void perf_mem_events__list(void);
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int perf_mem_events__record_args(const char **rec_argv, int *argv_nr,
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char **rec_tmp, int *tmp_nr);
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int perf_mem__tlb_scnprintf(char *out, size_t sz, struct mem_info *mem_info);
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int perf_mem__lvl_scnprintf(char *out, size_t sz, struct mem_info *mem_info);
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int perf_mem__snp_scnprintf(char *out, size_t sz, struct mem_info *mem_info);
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int perf_mem__lck_scnprintf(char *out, size_t sz, struct mem_info *mem_info);
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int perf_mem__blk_scnprintf(char *out, size_t sz, struct mem_info *mem_info);
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int perf_script__meminfo_scnprintf(char *bf, size_t size, struct mem_info *mem_info);
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struct c2c_stats {
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u32 nr_entries;
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u32 locks; /* count of 'lock' transactions */
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u32 store; /* count of all stores in trace */
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u32 st_uncache; /* stores to uncacheable address */
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u32 st_noadrs; /* cacheable store with no address */
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u32 st_l1hit; /* count of stores that hit L1D */
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u32 st_l1miss; /* count of stores that miss L1D */
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u32 st_na; /* count of stores with memory level is not available */
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u32 load; /* count of all loads in trace */
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u32 ld_excl; /* exclusive loads, rmt/lcl DRAM - snp none/miss */
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u32 ld_shared; /* shared loads, rmt/lcl DRAM - snp hit */
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u32 ld_uncache; /* loads to uncacheable address */
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u32 ld_io; /* loads to io address */
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u32 ld_miss; /* loads miss */
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u32 ld_noadrs; /* cacheable load with no address */
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u32 ld_fbhit; /* count of loads hitting Fill Buffer */
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u32 ld_l1hit; /* count of loads that hit L1D */
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u32 ld_l2hit; /* count of loads that hit L2D */
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u32 ld_llchit; /* count of loads that hit LLC */
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u32 lcl_hitm; /* count of loads with local HITM */
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u32 rmt_hitm; /* count of loads with remote HITM */
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u32 tot_hitm; /* count of loads with local and remote HITM */
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u32 rmt_hit; /* count of loads with remote hit clean; */
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u32 lcl_dram; /* count of loads miss to local DRAM */
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u32 rmt_dram; /* count of loads miss to remote DRAM */
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u32 blk_data; /* count of loads blocked by data */
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u32 blk_addr; /* count of loads blocked by address conflict */
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u32 nomap; /* count of load/stores with no phys addrs */
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u32 noparse; /* count of unparsable data sources */
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};
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struct hist_entry;
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int c2c_decode_stats(struct c2c_stats *stats, struct mem_info *mi);
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void c2c_add_stats(struct c2c_stats *stats, struct c2c_stats *add);
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#endif /* __PERF_MEM_EVENTS_H */
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