mirror of
https://mirrors.bfsu.edu.cn/git/linux.git
synced 2024-11-11 12:28:41 +08:00
162e134aed
Q: Do we have really have write buffer A: Yes, on newer Loongson processors there is a "store fill buffer" that will collect *cached* writes, on all Loongson processors AXI crossbar will buffer all writes. Q: Then why do we want to remove CPU_HAS_WB? A: Because CPU_HAS_WB introduces wbflush, which intends to flush all write reuqests to mmio device. We won't be affected by store fill buffer because it won't buffer uncached writes. And a regular memory barrier is sufficient to flush crossbar write buffer. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
24 lines
466 B
C
24 lines
466 B
C
// SPDX-License-Identifier: GPL-2.0-or-later
|
|
/*
|
|
* Copyright (C) 2007 Lemote Inc. & Institute of Computing Technology
|
|
* Author: Fuxin Zhang, zhangfx@lemote.com
|
|
*/
|
|
#include <linux/export.h>
|
|
#include <linux/init.h>
|
|
|
|
#include <asm/bootinfo.h>
|
|
#include <linux/libfdt.h>
|
|
#include <linux/of_fdt.h>
|
|
|
|
#include <asm/prom.h>
|
|
|
|
#include <loongson.h>
|
|
|
|
void *loongson_fdt_blob;
|
|
|
|
void __init plat_mem_setup(void)
|
|
{
|
|
if (loongson_fdt_blob)
|
|
__dt_setup_arch(loongson_fdt_blob);
|
|
}
|