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aee101d7b9
Commit314f6c23dd("powerpc/64s: Mask NIP before checking against SRR0") masked off the low 2 bits of the NIP value in the interrupt stack frame in case they are non-zero and mis-compare against a SRR0 register value of a CPU which always reads back 0 from the 2 low bits which are reserved. This now causes the opposite problem that an implementation which does implement those bits in SRR0 will mis-compare against the masked NIP value in which they have been cleared. QEMU is one such implementation, and this is allowed by the architecture. This can be triggered by sigfuz by setting low bits of PT_NIP in the signal context. Fix this for now by masking the SRR0 bits as well. Cleaner is probably to sanitise these values before putting them in registers or stack, but this is the quick and backportable fix. Fixes:314f6c23dd("powerpc/64s: Mask NIP before checking against SRR0") Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20220117134403.2995059-1-npiggin@gmail.com
730 lines
16 KiB
ArmAsm
730 lines
16 KiB
ArmAsm
#include <asm/asm-offsets.h>
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#include <asm/bug.h>
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#ifdef CONFIG_PPC_BOOK3S
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#include <asm/exception-64s.h>
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#else
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#include <asm/exception-64e.h>
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#endif
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#include <asm/feature-fixups.h>
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#include <asm/head-64.h>
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#include <asm/hw_irq.h>
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#include <asm/kup.h>
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#include <asm/mmu.h>
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#include <asm/ppc_asm.h>
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#include <asm/ptrace.h>
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.section ".toc","aw"
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SYS_CALL_TABLE:
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.tc sys_call_table[TC],sys_call_table
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#ifdef CONFIG_COMPAT
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COMPAT_SYS_CALL_TABLE:
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.tc compat_sys_call_table[TC],compat_sys_call_table
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#endif
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.previous
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.align 7
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.macro DEBUG_SRR_VALID srr
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#ifdef CONFIG_PPC_RFI_SRR_DEBUG
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.ifc \srr,srr
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mfspr r11,SPRN_SRR0
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ld r12,_NIP(r1)
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clrrdi r11,r11,2
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clrrdi r12,r12,2
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100: tdne r11,r12
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EMIT_WARN_ENTRY 100b,__FILE__,__LINE__,(BUGFLAG_WARNING | BUGFLAG_ONCE)
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mfspr r11,SPRN_SRR1
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ld r12,_MSR(r1)
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100: tdne r11,r12
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EMIT_WARN_ENTRY 100b,__FILE__,__LINE__,(BUGFLAG_WARNING | BUGFLAG_ONCE)
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.else
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mfspr r11,SPRN_HSRR0
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ld r12,_NIP(r1)
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clrrdi r11,r11,2
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clrrdi r12,r12,2
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100: tdne r11,r12
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EMIT_WARN_ENTRY 100b,__FILE__,__LINE__,(BUGFLAG_WARNING | BUGFLAG_ONCE)
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mfspr r11,SPRN_HSRR1
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ld r12,_MSR(r1)
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100: tdne r11,r12
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EMIT_WARN_ENTRY 100b,__FILE__,__LINE__,(BUGFLAG_WARNING | BUGFLAG_ONCE)
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.endif
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#endif
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.endm
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#ifdef CONFIG_PPC_BOOK3S
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.macro system_call_vectored name trapnr
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.globl system_call_vectored_\name
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system_call_vectored_\name:
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_ASM_NOKPROBE_SYMBOL(system_call_vectored_\name)
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SCV_INTERRUPT_TO_KERNEL
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mr r10,r1
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ld r1,PACAKSAVE(r13)
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std r10,0(r1)
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std r11,_NIP(r1)
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std r12,_MSR(r1)
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std r0,GPR0(r1)
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std r10,GPR1(r1)
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std r2,GPR2(r1)
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ld r2,PACATOC(r13)
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mfcr r12
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li r11,0
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/* Can we avoid saving r3-r8 in common case? */
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std r3,GPR3(r1)
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std r4,GPR4(r1)
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std r5,GPR5(r1)
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std r6,GPR6(r1)
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std r7,GPR7(r1)
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std r8,GPR8(r1)
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/* Zero r9-r12, this should only be required when restoring all GPRs */
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std r11,GPR9(r1)
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std r11,GPR10(r1)
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std r11,GPR11(r1)
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std r11,GPR12(r1)
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std r9,GPR13(r1)
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SAVE_NVGPRS(r1)
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std r11,_XER(r1)
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std r11,_LINK(r1)
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std r11,_CTR(r1)
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li r11,\trapnr
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std r11,_TRAP(r1)
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std r12,_CCR(r1)
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addi r10,r1,STACK_FRAME_OVERHEAD
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ld r11,exception_marker@toc(r2)
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std r11,-16(r10) /* "regshere" marker */
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BEGIN_FTR_SECTION
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HMT_MEDIUM
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END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
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/*
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* scv enters with MSR[EE]=1 and is immediately considered soft-masked.
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* The entry vector already sets PACAIRQSOFTMASK to IRQS_ALL_DISABLED,
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* and interrupts may be masked and pending already.
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* system_call_exception() will call trace_hardirqs_off() which means
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* interrupts could already have been blocked before trace_hardirqs_off,
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* but this is the best we can do.
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*/
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/* Calling convention has r9 = orig r0, r10 = regs */
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mr r9,r0
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bl system_call_exception
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.Lsyscall_vectored_\name\()_exit:
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addi r4,r1,STACK_FRAME_OVERHEAD
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li r5,1 /* scv */
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bl syscall_exit_prepare
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std r1,PACA_EXIT_SAVE_R1(r13) /* save r1 for restart */
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.Lsyscall_vectored_\name\()_rst_start:
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lbz r11,PACAIRQHAPPENED(r13)
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andi. r11,r11,(~PACA_IRQ_HARD_DIS)@l
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bne- syscall_vectored_\name\()_restart
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li r11,IRQS_ENABLED
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stb r11,PACAIRQSOFTMASK(r13)
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li r11,0
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stb r11,PACAIRQHAPPENED(r13) # clear out possible HARD_DIS
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ld r2,_CCR(r1)
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ld r4,_NIP(r1)
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ld r5,_MSR(r1)
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BEGIN_FTR_SECTION
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stdcx. r0,0,r1 /* to clear the reservation */
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END_FTR_SECTION_IFCLR(CPU_FTR_STCX_CHECKS_ADDRESS)
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BEGIN_FTR_SECTION
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HMT_MEDIUM_LOW
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END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
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cmpdi r3,0
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bne .Lsyscall_vectored_\name\()_restore_regs
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/* rfscv returns with LR->NIA and CTR->MSR */
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mtlr r4
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mtctr r5
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/* Could zero these as per ABI, but we may consider a stricter ABI
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* which preserves these if libc implementations can benefit, so
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* restore them for now until further measurement is done. */
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ld r0,GPR0(r1)
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ld r4,GPR4(r1)
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ld r5,GPR5(r1)
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ld r6,GPR6(r1)
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ld r7,GPR7(r1)
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ld r8,GPR8(r1)
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/* Zero volatile regs that may contain sensitive kernel data */
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li r9,0
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li r10,0
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li r11,0
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li r12,0
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mtspr SPRN_XER,r0
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/*
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* We don't need to restore AMR on the way back to userspace for KUAP.
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* The value of AMR only matters while we're in the kernel.
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*/
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mtcr r2
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REST_GPRS(2, 3, r1)
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REST_GPR(13, r1)
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REST_GPR(1, r1)
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RFSCV_TO_USER
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b . /* prevent speculative execution */
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.Lsyscall_vectored_\name\()_restore_regs:
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mtspr SPRN_SRR0,r4
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mtspr SPRN_SRR1,r5
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ld r3,_CTR(r1)
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ld r4,_LINK(r1)
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ld r5,_XER(r1)
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REST_NVGPRS(r1)
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ld r0,GPR0(r1)
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mtcr r2
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mtctr r3
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mtlr r4
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mtspr SPRN_XER,r5
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REST_GPRS(2, 13, r1)
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REST_GPR(1, r1)
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RFI_TO_USER
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.Lsyscall_vectored_\name\()_rst_end:
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syscall_vectored_\name\()_restart:
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_ASM_NOKPROBE_SYMBOL(syscall_vectored_\name\()_restart)
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GET_PACA(r13)
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ld r1,PACA_EXIT_SAVE_R1(r13)
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ld r2,PACATOC(r13)
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ld r3,RESULT(r1)
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addi r4,r1,STACK_FRAME_OVERHEAD
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li r11,IRQS_ALL_DISABLED
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stb r11,PACAIRQSOFTMASK(r13)
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bl syscall_exit_restart
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std r1,PACA_EXIT_SAVE_R1(r13) /* save r1 for restart */
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b .Lsyscall_vectored_\name\()_rst_start
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1:
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SOFT_MASK_TABLE(.Lsyscall_vectored_\name\()_rst_start, 1b)
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RESTART_TABLE(.Lsyscall_vectored_\name\()_rst_start, .Lsyscall_vectored_\name\()_rst_end, syscall_vectored_\name\()_restart)
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.endm
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system_call_vectored common 0x3000
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/*
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* We instantiate another entry copy for the SIGILL variant, with TRAP=0x7ff0
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* which is tested by system_call_exception when r0 is -1 (as set by vector
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* entry code).
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*/
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system_call_vectored sigill 0x7ff0
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/*
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* Entered via kernel return set up by kernel/sstep.c, must match entry regs
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*/
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.globl system_call_vectored_emulate
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system_call_vectored_emulate:
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_ASM_NOKPROBE_SYMBOL(system_call_vectored_emulate)
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li r10,IRQS_ALL_DISABLED
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stb r10,PACAIRQSOFTMASK(r13)
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b system_call_vectored_common
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#endif /* CONFIG_PPC_BOOK3S */
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.balign IFETCH_ALIGN_BYTES
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.globl system_call_common_real
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system_call_common_real:
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_ASM_NOKPROBE_SYMBOL(system_call_common_real)
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ld r10,PACAKMSR(r13) /* get MSR value for kernel */
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mtmsrd r10
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.balign IFETCH_ALIGN_BYTES
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.globl system_call_common
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system_call_common:
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_ASM_NOKPROBE_SYMBOL(system_call_common)
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mr r10,r1
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ld r1,PACAKSAVE(r13)
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std r10,0(r1)
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std r11,_NIP(r1)
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std r12,_MSR(r1)
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std r0,GPR0(r1)
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std r10,GPR1(r1)
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std r2,GPR2(r1)
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#ifdef CONFIG_PPC_FSL_BOOK3E
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START_BTB_FLUSH_SECTION
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BTB_FLUSH(r10)
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END_BTB_FLUSH_SECTION
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#endif
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ld r2,PACATOC(r13)
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mfcr r12
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li r11,0
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/* Can we avoid saving r3-r8 in common case? */
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std r3,GPR3(r1)
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std r4,GPR4(r1)
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std r5,GPR5(r1)
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std r6,GPR6(r1)
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std r7,GPR7(r1)
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std r8,GPR8(r1)
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/* Zero r9-r12, this should only be required when restoring all GPRs */
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std r11,GPR9(r1)
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std r11,GPR10(r1)
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std r11,GPR11(r1)
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std r11,GPR12(r1)
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std r9,GPR13(r1)
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SAVE_NVGPRS(r1)
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std r11,_XER(r1)
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std r11,_CTR(r1)
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mflr r10
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/*
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* This clears CR0.SO (bit 28), which is the error indication on
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* return from this system call.
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*/
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rldimi r12,r11,28,(63-28)
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li r11,0xc00
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std r10,_LINK(r1)
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std r11,_TRAP(r1)
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std r12,_CCR(r1)
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addi r10,r1,STACK_FRAME_OVERHEAD
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ld r11,exception_marker@toc(r2)
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std r11,-16(r10) /* "regshere" marker */
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#ifdef CONFIG_PPC_BOOK3S
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li r11,1
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stb r11,PACASRR_VALID(r13)
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#endif
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/*
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* We always enter kernel from userspace with irq soft-mask enabled and
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* nothing pending. system_call_exception() will call
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* trace_hardirqs_off().
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*/
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li r11,IRQS_ALL_DISABLED
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stb r11,PACAIRQSOFTMASK(r13)
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#ifdef CONFIG_PPC_BOOK3S
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li r12,-1 /* Set MSR_EE and MSR_RI */
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mtmsrd r12,1
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#else
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wrteei 1
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#endif
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/* Calling convention has r9 = orig r0, r10 = regs */
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mr r9,r0
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bl system_call_exception
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.Lsyscall_exit:
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addi r4,r1,STACK_FRAME_OVERHEAD
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li r5,0 /* !scv */
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bl syscall_exit_prepare
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std r1,PACA_EXIT_SAVE_R1(r13) /* save r1 for restart */
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#ifdef CONFIG_PPC_BOOK3S
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.Lsyscall_rst_start:
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lbz r11,PACAIRQHAPPENED(r13)
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andi. r11,r11,(~PACA_IRQ_HARD_DIS)@l
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bne- syscall_restart
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#endif
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li r11,IRQS_ENABLED
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stb r11,PACAIRQSOFTMASK(r13)
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li r11,0
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stb r11,PACAIRQHAPPENED(r13) # clear out possible HARD_DIS
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ld r2,_CCR(r1)
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ld r6,_LINK(r1)
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mtlr r6
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#ifdef CONFIG_PPC_BOOK3S
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lbz r4,PACASRR_VALID(r13)
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cmpdi r4,0
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bne 1f
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li r4,0
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stb r4,PACASRR_VALID(r13)
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#endif
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ld r4,_NIP(r1)
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ld r5,_MSR(r1)
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mtspr SPRN_SRR0,r4
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mtspr SPRN_SRR1,r5
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1:
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DEBUG_SRR_VALID srr
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BEGIN_FTR_SECTION
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stdcx. r0,0,r1 /* to clear the reservation */
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END_FTR_SECTION_IFCLR(CPU_FTR_STCX_CHECKS_ADDRESS)
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cmpdi r3,0
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bne .Lsyscall_restore_regs
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/* Zero volatile regs that may contain sensitive kernel data */
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li r0,0
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li r4,0
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li r5,0
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li r6,0
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li r7,0
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li r8,0
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li r9,0
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li r10,0
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li r11,0
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li r12,0
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mtctr r0
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mtspr SPRN_XER,r0
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.Lsyscall_restore_regs_cont:
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BEGIN_FTR_SECTION
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HMT_MEDIUM_LOW
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END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
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/*
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* We don't need to restore AMR on the way back to userspace for KUAP.
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* The value of AMR only matters while we're in the kernel.
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*/
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mtcr r2
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REST_GPRS(2, 3, r1)
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REST_GPR(13, r1)
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REST_GPR(1, r1)
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RFI_TO_USER
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b . /* prevent speculative execution */
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.Lsyscall_restore_regs:
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ld r3,_CTR(r1)
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ld r4,_XER(r1)
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REST_NVGPRS(r1)
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mtctr r3
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mtspr SPRN_XER,r4
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ld r0,GPR0(r1)
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REST_GPRS(4, 12, r1)
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b .Lsyscall_restore_regs_cont
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.Lsyscall_rst_end:
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#ifdef CONFIG_PPC_BOOK3S
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syscall_restart:
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_ASM_NOKPROBE_SYMBOL(syscall_restart)
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GET_PACA(r13)
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ld r1,PACA_EXIT_SAVE_R1(r13)
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ld r2,PACATOC(r13)
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ld r3,RESULT(r1)
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addi r4,r1,STACK_FRAME_OVERHEAD
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li r11,IRQS_ALL_DISABLED
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stb r11,PACAIRQSOFTMASK(r13)
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bl syscall_exit_restart
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std r1,PACA_EXIT_SAVE_R1(r13) /* save r1 for restart */
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b .Lsyscall_rst_start
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1:
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SOFT_MASK_TABLE(.Lsyscall_rst_start, 1b)
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RESTART_TABLE(.Lsyscall_rst_start, .Lsyscall_rst_end, syscall_restart)
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#endif
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/*
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* If MSR EE/RI was never enabled, IRQs not reconciled, NVGPRs not
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* touched, no exit work created, then this can be used.
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*/
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.balign IFETCH_ALIGN_BYTES
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.globl fast_interrupt_return_srr
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fast_interrupt_return_srr:
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_ASM_NOKPROBE_SYMBOL(fast_interrupt_return_srr)
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kuap_check_amr r3, r4
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ld r5,_MSR(r1)
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andi. r0,r5,MSR_PR
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#ifdef CONFIG_PPC_BOOK3S
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beq 1f
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kuap_user_restore r3, r4
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b .Lfast_user_interrupt_return_srr
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1: kuap_kernel_restore r3, r4
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andi. r0,r5,MSR_RI
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li r3,0 /* 0 return value, no EMULATE_STACK_STORE */
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bne+ .Lfast_kernel_interrupt_return_srr
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addi r3,r1,STACK_FRAME_OVERHEAD
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bl unrecoverable_exception
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b . /* should not get here */
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#else
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bne .Lfast_user_interrupt_return_srr
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b .Lfast_kernel_interrupt_return_srr
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#endif
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.macro interrupt_return_macro srr
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.balign IFETCH_ALIGN_BYTES
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.globl interrupt_return_\srr
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interrupt_return_\srr\():
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_ASM_NOKPROBE_SYMBOL(interrupt_return_\srr\())
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ld r4,_MSR(r1)
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andi. r0,r4,MSR_PR
|
|
beq interrupt_return_\srr\()_kernel
|
|
interrupt_return_\srr\()_user: /* make backtraces match the _kernel variant */
|
|
_ASM_NOKPROBE_SYMBOL(interrupt_return_\srr\()_user)
|
|
addi r3,r1,STACK_FRAME_OVERHEAD
|
|
bl interrupt_exit_user_prepare
|
|
cmpdi r3,0
|
|
bne- .Lrestore_nvgprs_\srr
|
|
.Lrestore_nvgprs_\srr\()_cont:
|
|
std r1,PACA_EXIT_SAVE_R1(r13) /* save r1 for restart */
|
|
#ifdef CONFIG_PPC_BOOK3S
|
|
.Linterrupt_return_\srr\()_user_rst_start:
|
|
lbz r11,PACAIRQHAPPENED(r13)
|
|
andi. r11,r11,(~PACA_IRQ_HARD_DIS)@l
|
|
bne- interrupt_return_\srr\()_user_restart
|
|
#endif
|
|
li r11,IRQS_ENABLED
|
|
stb r11,PACAIRQSOFTMASK(r13)
|
|
li r11,0
|
|
stb r11,PACAIRQHAPPENED(r13) # clear out possible HARD_DIS
|
|
|
|
.Lfast_user_interrupt_return_\srr\():
|
|
#ifdef CONFIG_PPC_BOOK3S
|
|
.ifc \srr,srr
|
|
lbz r4,PACASRR_VALID(r13)
|
|
.else
|
|
lbz r4,PACAHSRR_VALID(r13)
|
|
.endif
|
|
cmpdi r4,0
|
|
li r4,0
|
|
bne 1f
|
|
#endif
|
|
ld r11,_NIP(r1)
|
|
ld r12,_MSR(r1)
|
|
.ifc \srr,srr
|
|
mtspr SPRN_SRR0,r11
|
|
mtspr SPRN_SRR1,r12
|
|
1:
|
|
#ifdef CONFIG_PPC_BOOK3S
|
|
stb r4,PACASRR_VALID(r13)
|
|
#endif
|
|
.else
|
|
mtspr SPRN_HSRR0,r11
|
|
mtspr SPRN_HSRR1,r12
|
|
1:
|
|
#ifdef CONFIG_PPC_BOOK3S
|
|
stb r4,PACAHSRR_VALID(r13)
|
|
#endif
|
|
.endif
|
|
DEBUG_SRR_VALID \srr
|
|
|
|
#ifdef CONFIG_PPC_IRQ_SOFT_MASK_DEBUG
|
|
lbz r4,PACAIRQSOFTMASK(r13)
|
|
tdnei r4,IRQS_ENABLED
|
|
#endif
|
|
|
|
BEGIN_FTR_SECTION
|
|
ld r10,_PPR(r1)
|
|
mtspr SPRN_PPR,r10
|
|
END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
|
|
|
|
BEGIN_FTR_SECTION
|
|
stdcx. r0,0,r1 /* to clear the reservation */
|
|
FTR_SECTION_ELSE
|
|
ldarx r0,0,r1
|
|
ALT_FTR_SECTION_END_IFCLR(CPU_FTR_STCX_CHECKS_ADDRESS)
|
|
|
|
ld r3,_CCR(r1)
|
|
ld r4,_LINK(r1)
|
|
ld r5,_CTR(r1)
|
|
ld r6,_XER(r1)
|
|
li r0,0
|
|
|
|
REST_GPRS(7, 13, r1)
|
|
|
|
mtcr r3
|
|
mtlr r4
|
|
mtctr r5
|
|
mtspr SPRN_XER,r6
|
|
|
|
REST_GPRS(2, 6, r1)
|
|
REST_GPR(0, r1)
|
|
REST_GPR(1, r1)
|
|
.ifc \srr,srr
|
|
RFI_TO_USER
|
|
.else
|
|
HRFI_TO_USER
|
|
.endif
|
|
b . /* prevent speculative execution */
|
|
.Linterrupt_return_\srr\()_user_rst_end:
|
|
|
|
.Lrestore_nvgprs_\srr\():
|
|
REST_NVGPRS(r1)
|
|
b .Lrestore_nvgprs_\srr\()_cont
|
|
|
|
#ifdef CONFIG_PPC_BOOK3S
|
|
interrupt_return_\srr\()_user_restart:
|
|
_ASM_NOKPROBE_SYMBOL(interrupt_return_\srr\()_user_restart)
|
|
GET_PACA(r13)
|
|
ld r1,PACA_EXIT_SAVE_R1(r13)
|
|
ld r2,PACATOC(r13)
|
|
addi r3,r1,STACK_FRAME_OVERHEAD
|
|
li r11,IRQS_ALL_DISABLED
|
|
stb r11,PACAIRQSOFTMASK(r13)
|
|
bl interrupt_exit_user_restart
|
|
std r1,PACA_EXIT_SAVE_R1(r13) /* save r1 for restart */
|
|
b .Linterrupt_return_\srr\()_user_rst_start
|
|
1:
|
|
|
|
SOFT_MASK_TABLE(.Linterrupt_return_\srr\()_user_rst_start, 1b)
|
|
RESTART_TABLE(.Linterrupt_return_\srr\()_user_rst_start, .Linterrupt_return_\srr\()_user_rst_end, interrupt_return_\srr\()_user_restart)
|
|
#endif
|
|
|
|
.balign IFETCH_ALIGN_BYTES
|
|
interrupt_return_\srr\()_kernel:
|
|
_ASM_NOKPROBE_SYMBOL(interrupt_return_\srr\()_kernel)
|
|
addi r3,r1,STACK_FRAME_OVERHEAD
|
|
bl interrupt_exit_kernel_prepare
|
|
|
|
std r1,PACA_EXIT_SAVE_R1(r13) /* save r1 for restart */
|
|
.Linterrupt_return_\srr\()_kernel_rst_start:
|
|
ld r11,SOFTE(r1)
|
|
cmpwi r11,IRQS_ENABLED
|
|
stb r11,PACAIRQSOFTMASK(r13)
|
|
bne 1f
|
|
#ifdef CONFIG_PPC_BOOK3S
|
|
lbz r11,PACAIRQHAPPENED(r13)
|
|
andi. r11,r11,(~PACA_IRQ_HARD_DIS)@l
|
|
bne- interrupt_return_\srr\()_kernel_restart
|
|
#endif
|
|
li r11,0
|
|
stb r11,PACAIRQHAPPENED(r13) # clear out possible HARD_DIS
|
|
1:
|
|
|
|
.Lfast_kernel_interrupt_return_\srr\():
|
|
cmpdi cr1,r3,0
|
|
#ifdef CONFIG_PPC_BOOK3S
|
|
.ifc \srr,srr
|
|
lbz r4,PACASRR_VALID(r13)
|
|
.else
|
|
lbz r4,PACAHSRR_VALID(r13)
|
|
.endif
|
|
cmpdi r4,0
|
|
li r4,0
|
|
bne 1f
|
|
#endif
|
|
ld r11,_NIP(r1)
|
|
ld r12,_MSR(r1)
|
|
.ifc \srr,srr
|
|
mtspr SPRN_SRR0,r11
|
|
mtspr SPRN_SRR1,r12
|
|
1:
|
|
#ifdef CONFIG_PPC_BOOK3S
|
|
stb r4,PACASRR_VALID(r13)
|
|
#endif
|
|
.else
|
|
mtspr SPRN_HSRR0,r11
|
|
mtspr SPRN_HSRR1,r12
|
|
1:
|
|
#ifdef CONFIG_PPC_BOOK3S
|
|
stb r4,PACAHSRR_VALID(r13)
|
|
#endif
|
|
.endif
|
|
DEBUG_SRR_VALID \srr
|
|
|
|
BEGIN_FTR_SECTION
|
|
stdcx. r0,0,r1 /* to clear the reservation */
|
|
FTR_SECTION_ELSE
|
|
ldarx r0,0,r1
|
|
ALT_FTR_SECTION_END_IFCLR(CPU_FTR_STCX_CHECKS_ADDRESS)
|
|
|
|
ld r3,_LINK(r1)
|
|
ld r4,_CTR(r1)
|
|
ld r5,_XER(r1)
|
|
ld r6,_CCR(r1)
|
|
li r0,0
|
|
|
|
REST_GPRS(7, 12, r1)
|
|
|
|
mtlr r3
|
|
mtctr r4
|
|
mtspr SPRN_XER,r5
|
|
|
|
/*
|
|
* Leaving a stale exception_marker on the stack can confuse
|
|
* the reliable stack unwinder later on. Clear it.
|
|
*/
|
|
std r0,STACK_FRAME_OVERHEAD-16(r1)
|
|
|
|
REST_GPRS(2, 5, r1)
|
|
|
|
bne- cr1,1f /* emulate stack store */
|
|
mtcr r6
|
|
REST_GPR(6, r1)
|
|
REST_GPR(0, r1)
|
|
REST_GPR(1, r1)
|
|
.ifc \srr,srr
|
|
RFI_TO_KERNEL
|
|
.else
|
|
HRFI_TO_KERNEL
|
|
.endif
|
|
b . /* prevent speculative execution */
|
|
|
|
1: /*
|
|
* Emulate stack store with update. New r1 value was already calculated
|
|
* and updated in our interrupt regs by emulate_loadstore, but we can't
|
|
* store the previous value of r1 to the stack before re-loading our
|
|
* registers from it, otherwise they could be clobbered. Use
|
|
* PACA_EXGEN as temporary storage to hold the store data, as
|
|
* interrupts are disabled here so it won't be clobbered.
|
|
*/
|
|
mtcr r6
|
|
std r9,PACA_EXGEN+0(r13)
|
|
addi r9,r1,INT_FRAME_SIZE /* get original r1 */
|
|
REST_GPR(6, r1)
|
|
REST_GPR(0, r1)
|
|
REST_GPR(1, r1)
|
|
std r9,0(r1) /* perform store component of stdu */
|
|
ld r9,PACA_EXGEN+0(r13)
|
|
|
|
.ifc \srr,srr
|
|
RFI_TO_KERNEL
|
|
.else
|
|
HRFI_TO_KERNEL
|
|
.endif
|
|
b . /* prevent speculative execution */
|
|
.Linterrupt_return_\srr\()_kernel_rst_end:
|
|
|
|
#ifdef CONFIG_PPC_BOOK3S
|
|
interrupt_return_\srr\()_kernel_restart:
|
|
_ASM_NOKPROBE_SYMBOL(interrupt_return_\srr\()_kernel_restart)
|
|
GET_PACA(r13)
|
|
ld r1,PACA_EXIT_SAVE_R1(r13)
|
|
ld r2,PACATOC(r13)
|
|
addi r3,r1,STACK_FRAME_OVERHEAD
|
|
li r11,IRQS_ALL_DISABLED
|
|
stb r11,PACAIRQSOFTMASK(r13)
|
|
bl interrupt_exit_kernel_restart
|
|
std r1,PACA_EXIT_SAVE_R1(r13) /* save r1 for restart */
|
|
b .Linterrupt_return_\srr\()_kernel_rst_start
|
|
1:
|
|
|
|
SOFT_MASK_TABLE(.Linterrupt_return_\srr\()_kernel_rst_start, 1b)
|
|
RESTART_TABLE(.Linterrupt_return_\srr\()_kernel_rst_start, .Linterrupt_return_\srr\()_kernel_rst_end, interrupt_return_\srr\()_kernel_restart)
|
|
#endif
|
|
|
|
.endm
|
|
|
|
interrupt_return_macro srr
|
|
#ifdef CONFIG_PPC_BOOK3S
|
|
interrupt_return_macro hsrr
|
|
|
|
.globl __end_soft_masked
|
|
__end_soft_masked:
|
|
DEFINE_FIXED_SYMBOL(__end_soft_masked, text)
|
|
#endif /* CONFIG_PPC_BOOK3S */
|
|
|
|
#ifdef CONFIG_PPC_BOOK3S
|
|
_GLOBAL(ret_from_fork_scv)
|
|
bl schedule_tail
|
|
REST_NVGPRS(r1)
|
|
li r3,0 /* fork() return value */
|
|
b .Lsyscall_vectored_common_exit
|
|
#endif
|
|
|
|
_GLOBAL(ret_from_fork)
|
|
bl schedule_tail
|
|
REST_NVGPRS(r1)
|
|
li r3,0 /* fork() return value */
|
|
b .Lsyscall_exit
|
|
|
|
_GLOBAL(ret_from_kernel_thread)
|
|
bl schedule_tail
|
|
REST_NVGPRS(r1)
|
|
mtctr r14
|
|
mr r3,r15
|
|
#ifdef PPC64_ELF_ABI_v2
|
|
mr r12,r14
|
|
#endif
|
|
bctrl
|
|
li r3,0
|
|
b .Lsyscall_exit
|