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a811b420b6
This patch adds a set remote state SCM API. This will be used by the Venus and GPU subsystems to set state on the remote processors. This work was based on two patch sets by Jordan Crouse and Stanimir Varbanov. Signed-off-by: Andy Gross <andy.gross@linaro.org>
89 lines
2.9 KiB
C
89 lines
2.9 KiB
C
/* Copyright (c) 2010-2015, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __QCOM_SCM_INT_H
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#define __QCOM_SCM_INT_H
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#define QCOM_SCM_SVC_BOOT 0x1
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#define QCOM_SCM_BOOT_ADDR 0x1
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#define QCOM_SCM_BOOT_ADDR_MC 0x11
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#define QCOM_SCM_SET_REMOTE_STATE 0xa
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extern int __qcom_scm_set_remote_state(struct device *dev, u32 state, u32 id);
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#define QCOM_SCM_FLAG_HLOS 0x01
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#define QCOM_SCM_FLAG_COLDBOOT_MC 0x02
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#define QCOM_SCM_FLAG_WARMBOOT_MC 0x04
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extern int __qcom_scm_set_warm_boot_addr(struct device *dev, void *entry,
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const cpumask_t *cpus);
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extern int __qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus);
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#define QCOM_SCM_CMD_TERMINATE_PC 0x2
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#define QCOM_SCM_FLUSH_FLAG_MASK 0x3
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#define QCOM_SCM_CMD_CORE_HOTPLUGGED 0x10
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extern void __qcom_scm_cpu_power_down(u32 flags);
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#define QCOM_SCM_SVC_INFO 0x6
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#define QCOM_IS_CALL_AVAIL_CMD 0x1
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extern int __qcom_scm_is_call_available(struct device *dev, u32 svc_id,
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u32 cmd_id);
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#define QCOM_SCM_SVC_HDCP 0x11
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#define QCOM_SCM_CMD_HDCP 0x01
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extern int __qcom_scm_hdcp_req(struct device *dev,
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struct qcom_scm_hdcp_req *req, u32 req_cnt, u32 *resp);
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extern void __qcom_scm_init(void);
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#define QCOM_SCM_SVC_PIL 0x2
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#define QCOM_SCM_PAS_INIT_IMAGE_CMD 0x1
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#define QCOM_SCM_PAS_MEM_SETUP_CMD 0x2
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#define QCOM_SCM_PAS_AUTH_AND_RESET_CMD 0x5
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#define QCOM_SCM_PAS_SHUTDOWN_CMD 0x6
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#define QCOM_SCM_PAS_IS_SUPPORTED_CMD 0x7
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#define QCOM_SCM_PAS_MSS_RESET 0xa
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extern bool __qcom_scm_pas_supported(struct device *dev, u32 peripheral);
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extern int __qcom_scm_pas_init_image(struct device *dev, u32 peripheral,
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dma_addr_t metadata_phys);
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extern int __qcom_scm_pas_mem_setup(struct device *dev, u32 peripheral,
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phys_addr_t addr, phys_addr_t size);
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extern int __qcom_scm_pas_auth_and_reset(struct device *dev, u32 peripheral);
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extern int __qcom_scm_pas_shutdown(struct device *dev, u32 peripheral);
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extern int __qcom_scm_pas_mss_reset(struct device *dev, bool reset);
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/* common error codes */
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#define QCOM_SCM_V2_EBUSY -12
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#define QCOM_SCM_ENOMEM -5
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#define QCOM_SCM_EOPNOTSUPP -4
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#define QCOM_SCM_EINVAL_ADDR -3
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#define QCOM_SCM_EINVAL_ARG -2
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#define QCOM_SCM_ERROR -1
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#define QCOM_SCM_INTERRUPTED 1
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static inline int qcom_scm_remap_error(int err)
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{
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switch (err) {
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case QCOM_SCM_ERROR:
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return -EIO;
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case QCOM_SCM_EINVAL_ADDR:
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case QCOM_SCM_EINVAL_ARG:
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return -EINVAL;
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case QCOM_SCM_EOPNOTSUPP:
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return -EOPNOTSUPP;
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case QCOM_SCM_ENOMEM:
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return -ENOMEM;
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case QCOM_SCM_V2_EBUSY:
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return -EBUSY;
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}
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return -EINVAL;
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}
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#endif
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