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dfc9832ca3
As noted in recent discussions the name of the core clock for the PL022 derived SPI blocks is erroneously named in the U300 device tree. The kernel doesn't currently use the name, but may do so soon so let use rename all these clocks in accordance with the name given in the PL022 TRM (ARM DDI 0194G). Reviewed-by: Mark Brown <broonie@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
474 lines
11 KiB
Plaintext
474 lines
11 KiB
Plaintext
/*
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* Device Tree for the ST-Ericsson U300 Machine and SoC
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*/
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/dts-v1/;
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/include/ "skeleton.dtsi"
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/ {
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model = "ST-Ericsson U300";
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compatible = "stericsson,u300";
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#address-cells = <1>;
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#size-cells = <1>;
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chosen {
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bootargs = "root=/dev/ram0 console=ttyAMA0,115200n8 earlyprintk";
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};
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aliases {
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serial0 = &uart0;
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serial1 = &uart1;
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};
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memory {
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reg = <0x48000000 0x03c00000>;
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};
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s365 {
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compatible = "stericsson,s365";
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vana15-supply = <&ab3100_ldo_d_reg>;
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syscon = <&syscon>;
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};
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syscon: syscon@c0011000 {
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compatible = "stericsson,u300-syscon", "syscon";
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reg = <0xc0011000 0x1000>;
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clk32: app_32_clk@32k {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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};
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pll13: pll13@13M {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <13000000>;
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};
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/* Slow bridge clocks under PLL13 */
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slow_clk: slow_clk@13M {
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#clock-cells = <0>;
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compatible = "stericsson,u300-syscon-clk";
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clock-type = <0>; /* Slow */
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clock-id = <0>;
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clocks = <&pll13>;
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};
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uart0_clk: uart0_clk@13M {
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#clock-cells = <0>;
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compatible = "stericsson,u300-syscon-clk";
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clock-type = <0>; /* Slow */
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clock-id = <1>;
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clocks = <&slow_clk>;
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};
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gpio_clk: gpio_clk@13M {
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#clock-cells = <0>;
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compatible = "stericsson,u300-syscon-clk";
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clock-type = <0>; /* Slow */
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clock-id = <4>;
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clocks = <&slow_clk>;
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};
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rtc_clk: rtc_clk@13M {
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#clock-cells = <0>;
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compatible = "stericsson,u300-syscon-clk";
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clock-type = <0>; /* Slow */
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clock-id = <6>;
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clocks = <&slow_clk>;
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};
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apptimer_clk: app_tmr_clk@13M {
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#clock-cells = <0>;
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compatible = "stericsson,u300-syscon-clk";
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clock-type = <0>; /* Slow */
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clock-id = <7>;
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clocks = <&slow_clk>;
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};
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acc_tmr_clk@13M {
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#clock-cells = <0>;
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compatible = "stericsson,u300-syscon-clk";
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clock-type = <0>; /* Slow */
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clock-id = <8>;
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clocks = <&slow_clk>;
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};
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pll208: pll208@208M {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <208000000>;
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};
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app208: app_208_clk@208M {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clock-div = <1>;
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clock-mult = <1>;
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clocks = <&pll208>;
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};
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cpu_clk@208M {
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#clock-cells = <0>;
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compatible = "stericsson,u300-syscon-clk";
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clock-type = <2>; /* Rest */
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clock-id = <3>;
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clocks = <&app208>;
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};
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app104: app_104_clk@104M {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clock-div = <2>;
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clock-mult = <1>;
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clocks = <&pll208>;
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};
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semi_clk@104M {
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#clock-cells = <0>;
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compatible = "stericsson,u300-syscon-clk";
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clock-type = <2>; /* Rest */
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clock-id = <9>;
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clocks = <&app104>;
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};
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app52: app_52_clk@52M {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clock-div = <4>;
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clock-mult = <1>;
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clocks = <&pll208>;
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};
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/* AHB subsystem clocks */
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ahb_clk: ahb_subsys_clk@52M {
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#clock-cells = <0>;
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compatible = "stericsson,u300-syscon-clk";
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clock-type = <2>; /* Rest */
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clock-id = <10>;
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clocks = <&app52>;
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};
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intcon_clk@52M {
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#clock-cells = <0>;
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compatible = "stericsson,u300-syscon-clk";
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clock-type = <2>; /* Rest */
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clock-id = <12>;
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clocks = <&ahb_clk>;
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};
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emif_clk@52M {
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#clock-cells = <0>;
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compatible = "stericsson,u300-syscon-clk";
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clock-type = <2>; /* Rest */
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clock-id = <5>;
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clocks = <&ahb_clk>;
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};
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dmac_clk: dmac_clk@52M {
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#clock-cells = <0>;
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compatible = "stericsson,u300-syscon-clk";
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clock-type = <2>; /* Rest */
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clock-id = <4>;
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clocks = <&app52>;
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};
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fsmc_clk: fsmc_clk@52M {
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#clock-cells = <0>;
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compatible = "stericsson,u300-syscon-clk";
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clock-type = <2>; /* Rest */
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clock-id = <6>;
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clocks = <&app52>;
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};
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xgam_clk: xgam_clk@52M {
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#clock-cells = <0>;
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compatible = "stericsson,u300-syscon-clk";
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clock-type = <2>; /* Rest */
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clock-id = <8>;
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clocks = <&app52>;
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};
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app26: app_26_clk@26M {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clock-div = <2>;
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clock-mult = <1>;
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clocks = <&app52>;
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};
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/* Fast bridge clocks */
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fast_clk: fast_clk@26M {
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#clock-cells = <0>;
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compatible = "stericsson,u300-syscon-clk";
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clock-type = <1>; /* Fast */
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clock-id = <0>;
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clocks = <&app26>;
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};
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i2c0_clk: i2c0_clk@26M {
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#clock-cells = <0>;
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compatible = "stericsson,u300-syscon-clk";
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clock-type = <1>; /* Fast */
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clock-id = <1>;
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clocks = <&fast_clk>;
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};
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i2c1_clk: i2c1_clk@26M {
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#clock-cells = <0>;
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compatible = "stericsson,u300-syscon-clk";
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clock-type = <1>; /* Fast */
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clock-id = <2>;
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clocks = <&fast_clk>;
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};
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mmc_pclk: mmc_p_clk@26M {
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#clock-cells = <0>;
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compatible = "stericsson,u300-syscon-clk";
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clock-type = <1>; /* Fast */
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clock-id = <5>;
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clocks = <&fast_clk>;
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};
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mmc_mclk: mmc_mclk {
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#clock-cells = <0>;
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compatible = "stericsson,u300-syscon-mclk";
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clocks = <&mmc_pclk>;
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};
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spi_clk: spi_p_clk@26M {
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#clock-cells = <0>;
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compatible = "stericsson,u300-syscon-clk";
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clock-type = <1>; /* Fast */
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clock-id = <6>;
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clocks = <&fast_clk>;
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};
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};
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timer: timer@c0014000 {
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compatible = "stericsson,u300-apptimer";
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reg = <0xc0014000 0x1000>;
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interrupt-parent = <&vica>;
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interrupts = <24 25 26 27>;
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clocks = <&apptimer_clk>;
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};
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gpio: gpio@c0016000 {
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compatible = "stericsson,gpio-coh901";
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reg = <0xc0016000 0x1000>;
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interrupt-parent = <&vicb>;
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interrupts = <0 1 2 18 21 22 23>;
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clocks = <&gpio_clk>;
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interrupt-names = "gpio0", "gpio1", "gpio2", "gpio3",
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"gpio4", "gpio5", "gpio6";
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interrupt-controller;
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#interrupt-cells = <2>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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pinctrl: pinctrl@c0011000 {
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compatible = "stericsson,pinctrl-u300";
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reg = <0xc0011000 0x1000>;
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};
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watchdog: watchdog@c0012000 {
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compatible = "stericsson,coh901327";
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reg = <0xc0012000 0x1000>;
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interrupt-parent = <&vicb>;
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interrupts = <3>;
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clocks = <&clk32>;
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};
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rtc: rtc@c0017000 {
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compatible = "stericsson,coh901331";
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reg = <0xc0017000 0x1000>;
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interrupt-parent = <&vicb>;
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interrupts = <10>;
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clocks = <&rtc_clk>;
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};
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dmac: dma-controller@c00020000 {
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compatible = "stericsson,coh901318";
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reg = <0xc0020000 0x1000>;
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interrupt-parent = <&vica>;
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interrupts = <2>;
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#dma-cells = <1>;
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dma-channels = <40>;
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clocks = <&dmac_clk>;
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};
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/* A NAND flash of 128 MiB */
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fsmc: flash@40000000 {
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compatible = "stericsson,fsmc-nand";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x9f800000 0x1000>, /* FSMC Register*/
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<0x80000000 0x4000>, /* NAND Base DATA */
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<0x80020000 0x4000>, /* NAND Base ADDR */
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<0x80010000 0x4000>; /* NAND Base CMD */
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reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd";
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nand-skip-bbtscan;
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clocks = <&fsmc_clk>;
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partition@0 {
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label = "boot records";
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reg = <0x0 0x20000>;
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};
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partition@20000 {
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label = "free";
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reg = <0x20000 0x7e0000>;
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};
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partition@800000 {
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label = "platform";
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reg = <0x800000 0xf800000>;
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};
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};
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i2c0: i2c@c0004000 {
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compatible = "st,ddci2c";
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reg = <0xc0004000 0x1000>;
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interrupt-parent = <&vicb>;
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interrupts = <8>;
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clocks = <&i2c0_clk>;
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#address-cells = <1>;
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#size-cells = <0>;
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ab3100: ab3100@48 {
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compatible = "stericsson,ab3100";
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reg = <0x48>;
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interrupt-parent = <&vica>;
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interrupts = <0>; /* EXT0 IRQ */
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ab3100-regulators {
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compatible = "stericsson,ab3100-regulators";
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ab3100_ldo_a_reg: ab3100_ldo_a {
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regulator-compatible = "ab3100_ldo_a";
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startup-delay-us = <200>;
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regulator-always-on;
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regulator-boot-on;
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};
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ab3100_ldo_c_reg: ab3100_ldo_c {
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regulator-compatible = "ab3100_ldo_c";
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startup-delay-us = <200>;
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};
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ab3100_ldo_d_reg: ab3100_ldo_d {
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regulator-compatible = "ab3100_ldo_d";
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startup-delay-us = <200>;
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};
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ab3100_ldo_e_reg: ab3100_ldo_e {
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regulator-compatible = "ab3100_ldo_e";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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startup-delay-us = <200>;
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regulator-always-on;
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regulator-boot-on;
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};
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ab3100_ldo_f_reg: ab3100_ldo_f {
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regulator-compatible = "ab3100_ldo_f";
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regulator-min-microvolt = <2500000>;
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regulator-max-microvolt = <2500000>;
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startup-delay-us = <600>;
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regulator-always-on;
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regulator-boot-on;
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};
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ab3100_ldo_g_reg: ab3100_ldo_g {
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regulator-compatible = "ab3100_ldo_g";
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regulator-min-microvolt = <1500000>;
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regulator-max-microvolt = <2850000>;
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startup-delay-us = <400>;
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};
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ab3100_ldo_h_reg: ab3100_ldo_h {
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regulator-compatible = "ab3100_ldo_h";
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regulator-min-microvolt = <1200000>;
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regulator-max-microvolt = <2750000>;
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startup-delay-us = <200>;
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};
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ab3100_ldo_k_reg: ab3100_ldo_k {
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regulator-compatible = "ab3100_ldo_k";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <2750000>;
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startup-delay-us = <200>;
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};
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ab3100_ext_reg: ab3100_ext {
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regulator-compatible = "ab3100_ext";
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};
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ab3100_buck_reg: ab3100_buck {
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regulator-compatible = "ab3100_buck";
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regulator-min-microvolt = <1200000>;
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regulator-max-microvolt = <1800000>;
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startup-delay-us = <1000>;
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regulator-always-on;
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regulator-boot-on;
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};
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};
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};
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};
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i2c1: i2c@c0005000 {
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compatible = "st,ddci2c";
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reg = <0xc0005000 0x1000>;
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interrupt-parent = <&vicb>;
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interrupts = <9>;
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clocks = <&i2c1_clk>;
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#address-cells = <1>;
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#size-cells = <0>;
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fwcam0: fwcam@10 {
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reg = <0x10>;
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};
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fwcam1: fwcam@5d {
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reg = <0x5d>;
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};
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};
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amba {
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compatible = "arm,amba-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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vica: interrupt-controller@a0001000 {
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compatible = "arm,versatile-vic";
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interrupt-controller;
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#interrupt-cells = <1>;
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reg = <0xa0001000 0x20>;
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};
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vicb: interrupt-controller@a0002000 {
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compatible = "arm,versatile-vic";
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interrupt-controller;
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#interrupt-cells = <1>;
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reg = <0xa0002000 0x20>;
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};
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uart0: serial@c0013000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0xc0013000 0x1000>;
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interrupt-parent = <&vica>;
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interrupts = <22>;
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clocks = <&uart0_clk>, <&uart0_clk>;
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clock-names = "apb_pclk", "uart0_clk";
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dmas = <&dmac 17 &dmac 18>;
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dma-names = "tx", "rx";
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};
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uart1: serial@c0007000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0xc0007000 0x1000>;
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interrupt-parent = <&vicb>;
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interrupts = <20>;
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dmas = <&dmac 38 &dmac 39>;
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dma-names = "tx", "rx";
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};
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mmcsd: mmcsd@c0001000 {
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compatible = "arm,pl18x", "arm,primecell";
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reg = <0xc0001000 0x1000>;
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interrupt-parent = <&vicb>;
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interrupts = <6 7>;
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clocks = <&mmc_pclk>, <&mmc_mclk>;
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clock-names = "apb_pclk", "mclk";
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max-frequency = <24000000>;
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bus-width = <4>; // SD-card slot
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mmc-cap-mmc-highspeed;
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mmc-cap-sd-highspeed;
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cd-gpios = <&gpio 12 0x4>;
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cd-inverted;
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vmmc-supply = <&ab3100_ldo_g_reg>;
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dmas = <&dmac 14>;
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dma-names = "rx";
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};
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spi: ssp@c0006000 {
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compatible = "arm,pl022", "arm,primecell";
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reg = <0xc0006000 0x1000>;
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interrupt-parent = <&vica>;
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interrupts = <23>;
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clocks = <&spi_clk>, <&spi_clk>;
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clock-names = "SSPCLK", "apb_pclk";
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dmas = <&dmac 27 &dmac 28>;
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dma-names = "tx", "rx";
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num-cs = <3>;
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#address-cells = <1>;
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#size-cells = <0>;
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spi-dummy@1 {
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compatible = "arm,pl022-dummy";
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reg = <1>;
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spi-max-frequency = <20000000>;
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};
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};
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};
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};
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