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9a434cee77
Dynamically support SMCCCC and legacy conventions by detecting which convention to use at runtime. qcom_scm_call_atomic and qcom_scm_call can then be moved in qcom_scm.c and use underlying convention backend as appropriate. Thus, rename qcom_scm-64,-32 to reflect that they are backends for -smc and -legacy, respectively. Also add support for making SCM calls earlier than when SCM driver probes to support use cases such as qcom_scm_set_cold_boot_addr. Support is added by lazily initializing the convention and guarding the query with a spin lock. The limitation of these early SCM calls is that they cannot use DMA, as in the case of >4 arguments for SMC convention and any non-atomic call for legacy convention. Tested-by: Brian Masney <masneyb@onstation.org> # arm32 Tested-by: Stephan Gerhold <stephan@gerhold.net> Signed-off-by: Elliot Berman <eberman@codeaurora.org> Link: https://lore.kernel.org/r/1578431066-19600-18-git-send-email-eberman@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
152 lines
3.7 KiB
C
152 lines
3.7 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/* Copyright (c) 2015,2019 The Linux Foundation. All rights reserved.
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*/
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#include <linux/io.h>
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#include <linux/errno.h>
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#include <linux/delay.h>
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#include <linux/mutex.h>
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#include <linux/slab.h>
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#include <linux/types.h>
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#include <linux/qcom_scm.h>
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#include <linux/arm-smccc.h>
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#include <linux/dma-mapping.h>
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#include "qcom_scm.h"
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/**
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* struct arm_smccc_args
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* @args: The array of values used in registers in smc instruction
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*/
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struct arm_smccc_args {
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unsigned long args[8];
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};
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static DEFINE_MUTEX(qcom_scm_lock);
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#define QCOM_SCM_EBUSY_WAIT_MS 30
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#define QCOM_SCM_EBUSY_MAX_RETRY 20
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#define SCM_SMC_N_REG_ARGS 4
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#define SCM_SMC_FIRST_EXT_IDX (SCM_SMC_N_REG_ARGS - 1)
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#define SCM_SMC_N_EXT_ARGS (MAX_QCOM_SCM_ARGS - SCM_SMC_N_REG_ARGS + 1)
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#define SCM_SMC_FIRST_REG_IDX 2
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#define SCM_SMC_LAST_REG_IDX (SCM_SMC_FIRST_REG_IDX + SCM_SMC_N_REG_ARGS - 1)
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static void __scm_smc_do_quirk(const struct arm_smccc_args *smc,
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struct arm_smccc_res *res)
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{
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unsigned long a0 = smc->args[0];
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struct arm_smccc_quirk quirk = { .id = ARM_SMCCC_QUIRK_QCOM_A6 };
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quirk.state.a6 = 0;
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do {
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arm_smccc_smc_quirk(a0, smc->args[1], smc->args[2],
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smc->args[3], smc->args[4], smc->args[5],
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quirk.state.a6, smc->args[7], res, &quirk);
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if (res->a0 == QCOM_SCM_INTERRUPTED)
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a0 = res->a0;
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} while (res->a0 == QCOM_SCM_INTERRUPTED);
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}
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static void __scm_smc_do(const struct arm_smccc_args *smc,
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struct arm_smccc_res *res, bool atomic)
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{
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int retry_count = 0;
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if (atomic) {
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__scm_smc_do_quirk(smc, res);
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return;
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}
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do {
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mutex_lock(&qcom_scm_lock);
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__scm_smc_do_quirk(smc, res);
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mutex_unlock(&qcom_scm_lock);
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if (res->a0 == QCOM_SCM_V2_EBUSY) {
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if (retry_count++ > QCOM_SCM_EBUSY_MAX_RETRY)
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break;
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msleep(QCOM_SCM_EBUSY_WAIT_MS);
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}
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} while (res->a0 == QCOM_SCM_V2_EBUSY);
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}
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int scm_smc_call(struct device *dev, const struct qcom_scm_desc *desc,
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struct qcom_scm_res *res, bool atomic)
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{
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int arglen = desc->arginfo & 0xf;
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int i;
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dma_addr_t args_phys = 0;
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void *args_virt = NULL;
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size_t alloc_len;
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gfp_t flag = atomic ? GFP_ATOMIC : GFP_KERNEL;
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u32 smccc_call_type = atomic ? ARM_SMCCC_FAST_CALL : ARM_SMCCC_STD_CALL;
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u32 qcom_smccc_convention =
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(qcom_scm_convention == SMC_CONVENTION_ARM_32) ?
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ARM_SMCCC_SMC_32 : ARM_SMCCC_SMC_64;
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struct arm_smccc_res smc_res;
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struct arm_smccc_args smc = {0};
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smc.args[0] = ARM_SMCCC_CALL_VAL(
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smccc_call_type,
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qcom_smccc_convention,
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desc->owner,
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SCM_SMC_FNID(desc->svc, desc->cmd));
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smc.args[1] = desc->arginfo;
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for (i = 0; i < SCM_SMC_N_REG_ARGS; i++)
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smc.args[i + SCM_SMC_FIRST_REG_IDX] = desc->args[i];
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if (unlikely(arglen > SCM_SMC_N_REG_ARGS)) {
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alloc_len = SCM_SMC_N_EXT_ARGS * sizeof(u64);
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args_virt = kzalloc(PAGE_ALIGN(alloc_len), flag);
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if (!args_virt)
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return -ENOMEM;
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if (qcom_smccc_convention == ARM_SMCCC_SMC_32) {
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__le32 *args = args_virt;
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for (i = 0; i < SCM_SMC_N_EXT_ARGS; i++)
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args[i] = cpu_to_le32(desc->args[i +
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SCM_SMC_FIRST_EXT_IDX]);
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} else {
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__le64 *args = args_virt;
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for (i = 0; i < SCM_SMC_N_EXT_ARGS; i++)
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args[i] = cpu_to_le64(desc->args[i +
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SCM_SMC_FIRST_EXT_IDX]);
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}
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args_phys = dma_map_single(dev, args_virt, alloc_len,
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DMA_TO_DEVICE);
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if (dma_mapping_error(dev, args_phys)) {
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kfree(args_virt);
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return -ENOMEM;
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}
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smc.args[SCM_SMC_LAST_REG_IDX] = args_phys;
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}
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__scm_smc_do(&smc, &smc_res, atomic);
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if (args_virt) {
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dma_unmap_single(dev, args_phys, alloc_len, DMA_TO_DEVICE);
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kfree(args_virt);
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}
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if (res) {
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res->result[0] = smc_res.a1;
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res->result[1] = smc_res.a2;
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res->result[2] = smc_res.a3;
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}
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return (long)smc_res.a0 ? qcom_scm_remap_error(smc_res.a0) : 0;
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}
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