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d49e6ee2d6
The count_read and count_write callbacks are simplified to pass val as unsigned long rather than as an opaque data structure. The opaque counter_count_read_value and counter_count_write_value structures, counter_count_value_type enum, and relevant counter_count_read_value_set and counter_count_write_value_get functions, are removed as they are no longer used. Cc: Patrick Havelange <patrick.havelange@essensium.com> Acked-by: Fabrice Gasnier <fabrice.gasnier@st.com> Acked-by: David Lechner <david@lechnology.com> Signed-off-by: William Breathitt Gray <vilhelm.gray@gmail.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
754 lines
18 KiB
C
754 lines
18 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* STM32 Low-Power Timer Encoder and Counter driver
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*
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* Copyright (C) STMicroelectronics 2017
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*
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* Author: Fabrice Gasnier <fabrice.gasnier@st.com>
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*
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* Inspired by 104-quad-8 and stm32-timer-trigger drivers.
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*
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*/
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#include <linux/bitfield.h>
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#include <linux/counter.h>
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#include <linux/iio/iio.h>
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#include <linux/mfd/stm32-lptimer.h>
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#include <linux/module.h>
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#include <linux/pinctrl/consumer.h>
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#include <linux/platform_device.h>
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struct stm32_lptim_cnt {
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struct counter_device counter;
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struct device *dev;
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struct regmap *regmap;
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struct clk *clk;
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u32 ceiling;
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u32 polarity;
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u32 quadrature_mode;
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bool enabled;
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};
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static int stm32_lptim_is_enabled(struct stm32_lptim_cnt *priv)
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{
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u32 val;
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int ret;
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ret = regmap_read(priv->regmap, STM32_LPTIM_CR, &val);
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if (ret)
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return ret;
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return FIELD_GET(STM32_LPTIM_ENABLE, val);
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}
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static int stm32_lptim_set_enable_state(struct stm32_lptim_cnt *priv,
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int enable)
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{
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int ret;
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u32 val;
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val = FIELD_PREP(STM32_LPTIM_ENABLE, enable);
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ret = regmap_write(priv->regmap, STM32_LPTIM_CR, val);
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if (ret)
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return ret;
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if (!enable) {
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clk_disable(priv->clk);
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priv->enabled = false;
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return 0;
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}
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/* LP timer must be enabled before writing CMP & ARR */
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ret = regmap_write(priv->regmap, STM32_LPTIM_ARR, priv->ceiling);
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if (ret)
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return ret;
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ret = regmap_write(priv->regmap, STM32_LPTIM_CMP, 0);
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if (ret)
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return ret;
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/* ensure CMP & ARR registers are properly written */
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ret = regmap_read_poll_timeout(priv->regmap, STM32_LPTIM_ISR, val,
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(val & STM32_LPTIM_CMPOK_ARROK),
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100, 1000);
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if (ret)
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return ret;
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ret = regmap_write(priv->regmap, STM32_LPTIM_ICR,
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STM32_LPTIM_CMPOKCF_ARROKCF);
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if (ret)
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return ret;
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ret = clk_enable(priv->clk);
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if (ret) {
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regmap_write(priv->regmap, STM32_LPTIM_CR, 0);
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return ret;
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}
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priv->enabled = true;
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/* Start LP timer in continuous mode */
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return regmap_update_bits(priv->regmap, STM32_LPTIM_CR,
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STM32_LPTIM_CNTSTRT, STM32_LPTIM_CNTSTRT);
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}
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static int stm32_lptim_setup(struct stm32_lptim_cnt *priv, int enable)
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{
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u32 mask = STM32_LPTIM_ENC | STM32_LPTIM_COUNTMODE |
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STM32_LPTIM_CKPOL | STM32_LPTIM_PRESC;
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u32 val;
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/* Setup LP timer encoder/counter and polarity, without prescaler */
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if (priv->quadrature_mode)
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val = enable ? STM32_LPTIM_ENC : 0;
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else
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val = enable ? STM32_LPTIM_COUNTMODE : 0;
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val |= FIELD_PREP(STM32_LPTIM_CKPOL, enable ? priv->polarity : 0);
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return regmap_update_bits(priv->regmap, STM32_LPTIM_CFGR, mask, val);
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}
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static int stm32_lptim_write_raw(struct iio_dev *indio_dev,
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struct iio_chan_spec const *chan,
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int val, int val2, long mask)
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{
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struct stm32_lptim_cnt *priv = iio_priv(indio_dev);
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int ret;
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switch (mask) {
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case IIO_CHAN_INFO_ENABLE:
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if (val < 0 || val > 1)
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return -EINVAL;
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/* Check nobody uses the timer, or already disabled/enabled */
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ret = stm32_lptim_is_enabled(priv);
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if ((ret < 0) || (!ret && !val))
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return ret;
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if (val && ret)
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return -EBUSY;
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ret = stm32_lptim_setup(priv, val);
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if (ret)
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return ret;
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return stm32_lptim_set_enable_state(priv, val);
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default:
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return -EINVAL;
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}
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}
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static int stm32_lptim_read_raw(struct iio_dev *indio_dev,
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struct iio_chan_spec const *chan,
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int *val, int *val2, long mask)
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{
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struct stm32_lptim_cnt *priv = iio_priv(indio_dev);
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u32 dat;
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int ret;
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switch (mask) {
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case IIO_CHAN_INFO_RAW:
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ret = regmap_read(priv->regmap, STM32_LPTIM_CNT, &dat);
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if (ret)
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return ret;
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*val = dat;
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return IIO_VAL_INT;
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case IIO_CHAN_INFO_ENABLE:
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ret = stm32_lptim_is_enabled(priv);
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if (ret < 0)
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return ret;
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*val = ret;
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return IIO_VAL_INT;
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case IIO_CHAN_INFO_SCALE:
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/* Non-quadrature mode: scale = 1 */
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*val = 1;
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*val2 = 0;
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if (priv->quadrature_mode) {
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/*
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* Quadrature encoder mode:
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* - both edges, quarter cycle, scale is 0.25
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* - either rising/falling edge scale is 0.5
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*/
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if (priv->polarity > 1)
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*val2 = 2;
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else
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*val2 = 1;
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}
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return IIO_VAL_FRACTIONAL_LOG2;
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default:
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return -EINVAL;
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}
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}
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static const struct iio_info stm32_lptim_cnt_iio_info = {
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.read_raw = stm32_lptim_read_raw,
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.write_raw = stm32_lptim_write_raw,
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};
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static const char *const stm32_lptim_quadrature_modes[] = {
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"non-quadrature",
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"quadrature",
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};
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static int stm32_lptim_get_quadrature_mode(struct iio_dev *indio_dev,
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const struct iio_chan_spec *chan)
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{
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struct stm32_lptim_cnt *priv = iio_priv(indio_dev);
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return priv->quadrature_mode;
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}
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static int stm32_lptim_set_quadrature_mode(struct iio_dev *indio_dev,
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const struct iio_chan_spec *chan,
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unsigned int type)
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{
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struct stm32_lptim_cnt *priv = iio_priv(indio_dev);
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if (stm32_lptim_is_enabled(priv))
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return -EBUSY;
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priv->quadrature_mode = type;
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return 0;
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}
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static const struct iio_enum stm32_lptim_quadrature_mode_en = {
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.items = stm32_lptim_quadrature_modes,
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.num_items = ARRAY_SIZE(stm32_lptim_quadrature_modes),
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.get = stm32_lptim_get_quadrature_mode,
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.set = stm32_lptim_set_quadrature_mode,
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};
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static const char * const stm32_lptim_cnt_polarity[] = {
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"rising-edge", "falling-edge", "both-edges",
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};
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static int stm32_lptim_cnt_get_polarity(struct iio_dev *indio_dev,
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const struct iio_chan_spec *chan)
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{
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struct stm32_lptim_cnt *priv = iio_priv(indio_dev);
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return priv->polarity;
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}
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static int stm32_lptim_cnt_set_polarity(struct iio_dev *indio_dev,
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const struct iio_chan_spec *chan,
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unsigned int type)
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{
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struct stm32_lptim_cnt *priv = iio_priv(indio_dev);
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if (stm32_lptim_is_enabled(priv))
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return -EBUSY;
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priv->polarity = type;
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return 0;
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}
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static const struct iio_enum stm32_lptim_cnt_polarity_en = {
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.items = stm32_lptim_cnt_polarity,
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.num_items = ARRAY_SIZE(stm32_lptim_cnt_polarity),
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.get = stm32_lptim_cnt_get_polarity,
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.set = stm32_lptim_cnt_set_polarity,
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};
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static ssize_t stm32_lptim_cnt_get_ceiling(struct stm32_lptim_cnt *priv,
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char *buf)
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{
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return snprintf(buf, PAGE_SIZE, "%u\n", priv->ceiling);
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}
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static ssize_t stm32_lptim_cnt_set_ceiling(struct stm32_lptim_cnt *priv,
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const char *buf, size_t len)
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{
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int ret;
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if (stm32_lptim_is_enabled(priv))
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return -EBUSY;
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ret = kstrtouint(buf, 0, &priv->ceiling);
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if (ret)
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return ret;
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if (priv->ceiling > STM32_LPTIM_MAX_ARR)
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return -EINVAL;
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return len;
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}
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static ssize_t stm32_lptim_cnt_get_preset_iio(struct iio_dev *indio_dev,
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uintptr_t private,
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const struct iio_chan_spec *chan,
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char *buf)
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{
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struct stm32_lptim_cnt *priv = iio_priv(indio_dev);
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return stm32_lptim_cnt_get_ceiling(priv, buf);
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}
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static ssize_t stm32_lptim_cnt_set_preset_iio(struct iio_dev *indio_dev,
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uintptr_t private,
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const struct iio_chan_spec *chan,
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const char *buf, size_t len)
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{
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struct stm32_lptim_cnt *priv = iio_priv(indio_dev);
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return stm32_lptim_cnt_set_ceiling(priv, buf, len);
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}
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/* LP timer with encoder */
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static const struct iio_chan_spec_ext_info stm32_lptim_enc_ext_info[] = {
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{
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.name = "preset",
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.shared = IIO_SEPARATE,
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.read = stm32_lptim_cnt_get_preset_iio,
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.write = stm32_lptim_cnt_set_preset_iio,
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},
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IIO_ENUM("polarity", IIO_SEPARATE, &stm32_lptim_cnt_polarity_en),
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IIO_ENUM_AVAILABLE("polarity", &stm32_lptim_cnt_polarity_en),
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IIO_ENUM("quadrature_mode", IIO_SEPARATE,
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&stm32_lptim_quadrature_mode_en),
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IIO_ENUM_AVAILABLE("quadrature_mode", &stm32_lptim_quadrature_mode_en),
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{}
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};
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static const struct iio_chan_spec stm32_lptim_enc_channels = {
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.type = IIO_COUNT,
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.channel = 0,
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.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
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BIT(IIO_CHAN_INFO_ENABLE) |
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BIT(IIO_CHAN_INFO_SCALE),
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.ext_info = stm32_lptim_enc_ext_info,
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.indexed = 1,
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};
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/* LP timer without encoder (counter only) */
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static const struct iio_chan_spec_ext_info stm32_lptim_cnt_ext_info[] = {
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{
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.name = "preset",
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.shared = IIO_SEPARATE,
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.read = stm32_lptim_cnt_get_preset_iio,
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.write = stm32_lptim_cnt_set_preset_iio,
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},
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IIO_ENUM("polarity", IIO_SEPARATE, &stm32_lptim_cnt_polarity_en),
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IIO_ENUM_AVAILABLE("polarity", &stm32_lptim_cnt_polarity_en),
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{}
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};
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static const struct iio_chan_spec stm32_lptim_cnt_channels = {
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.type = IIO_COUNT,
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.channel = 0,
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.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
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BIT(IIO_CHAN_INFO_ENABLE) |
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BIT(IIO_CHAN_INFO_SCALE),
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.ext_info = stm32_lptim_cnt_ext_info,
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.indexed = 1,
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};
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/**
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* enum stm32_lptim_cnt_function - enumerates LPTimer counter & encoder modes
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* @STM32_LPTIM_COUNTER_INCREASE: up count on IN1 rising, falling or both edges
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* @STM32_LPTIM_ENCODER_BOTH_EDGE: count on both edges (IN1 & IN2 quadrature)
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*/
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enum stm32_lptim_cnt_function {
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STM32_LPTIM_COUNTER_INCREASE,
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STM32_LPTIM_ENCODER_BOTH_EDGE,
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};
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static enum counter_count_function stm32_lptim_cnt_functions[] = {
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[STM32_LPTIM_COUNTER_INCREASE] = COUNTER_COUNT_FUNCTION_INCREASE,
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[STM32_LPTIM_ENCODER_BOTH_EDGE] = COUNTER_COUNT_FUNCTION_QUADRATURE_X4,
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};
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enum stm32_lptim_synapse_action {
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STM32_LPTIM_SYNAPSE_ACTION_RISING_EDGE,
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STM32_LPTIM_SYNAPSE_ACTION_FALLING_EDGE,
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STM32_LPTIM_SYNAPSE_ACTION_BOTH_EDGES,
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STM32_LPTIM_SYNAPSE_ACTION_NONE,
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};
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static enum counter_synapse_action stm32_lptim_cnt_synapse_actions[] = {
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/* Index must match with stm32_lptim_cnt_polarity[] (priv->polarity) */
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[STM32_LPTIM_SYNAPSE_ACTION_RISING_EDGE] = COUNTER_SYNAPSE_ACTION_RISING_EDGE,
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[STM32_LPTIM_SYNAPSE_ACTION_FALLING_EDGE] = COUNTER_SYNAPSE_ACTION_FALLING_EDGE,
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[STM32_LPTIM_SYNAPSE_ACTION_BOTH_EDGES] = COUNTER_SYNAPSE_ACTION_BOTH_EDGES,
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[STM32_LPTIM_SYNAPSE_ACTION_NONE] = COUNTER_SYNAPSE_ACTION_NONE,
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};
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static int stm32_lptim_cnt_read(struct counter_device *counter,
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struct counter_count *count, unsigned long *val)
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{
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struct stm32_lptim_cnt *const priv = counter->priv;
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u32 cnt;
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int ret;
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ret = regmap_read(priv->regmap, STM32_LPTIM_CNT, &cnt);
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if (ret)
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return ret;
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*val = cnt;
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return 0;
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}
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static int stm32_lptim_cnt_function_get(struct counter_device *counter,
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struct counter_count *count,
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size_t *function)
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{
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struct stm32_lptim_cnt *const priv = counter->priv;
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if (!priv->quadrature_mode) {
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*function = STM32_LPTIM_COUNTER_INCREASE;
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return 0;
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}
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if (priv->polarity == STM32_LPTIM_SYNAPSE_ACTION_BOTH_EDGES) {
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*function = STM32_LPTIM_ENCODER_BOTH_EDGE;
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return 0;
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}
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return -EINVAL;
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}
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static int stm32_lptim_cnt_function_set(struct counter_device *counter,
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struct counter_count *count,
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size_t function)
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{
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struct stm32_lptim_cnt *const priv = counter->priv;
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if (stm32_lptim_is_enabled(priv))
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return -EBUSY;
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switch (function) {
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case STM32_LPTIM_COUNTER_INCREASE:
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priv->quadrature_mode = 0;
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return 0;
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case STM32_LPTIM_ENCODER_BOTH_EDGE:
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priv->quadrature_mode = 1;
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priv->polarity = STM32_LPTIM_SYNAPSE_ACTION_BOTH_EDGES;
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return 0;
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}
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return -EINVAL;
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}
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static ssize_t stm32_lptim_cnt_enable_read(struct counter_device *counter,
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struct counter_count *count,
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void *private, char *buf)
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{
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struct stm32_lptim_cnt *const priv = counter->priv;
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int ret;
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ret = stm32_lptim_is_enabled(priv);
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if (ret < 0)
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return ret;
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return scnprintf(buf, PAGE_SIZE, "%u\n", ret);
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}
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static ssize_t stm32_lptim_cnt_enable_write(struct counter_device *counter,
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struct counter_count *count,
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void *private,
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const char *buf, size_t len)
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{
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struct stm32_lptim_cnt *const priv = counter->priv;
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bool enable;
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int ret;
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ret = kstrtobool(buf, &enable);
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if (ret)
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return ret;
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/* Check nobody uses the timer, or already disabled/enabled */
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ret = stm32_lptim_is_enabled(priv);
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if ((ret < 0) || (!ret && !enable))
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return ret;
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if (enable && ret)
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return -EBUSY;
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ret = stm32_lptim_setup(priv, enable);
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if (ret)
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return ret;
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ret = stm32_lptim_set_enable_state(priv, enable);
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if (ret)
|
|
return ret;
|
|
|
|
return len;
|
|
}
|
|
|
|
static ssize_t stm32_lptim_cnt_ceiling_read(struct counter_device *counter,
|
|
struct counter_count *count,
|
|
void *private, char *buf)
|
|
{
|
|
struct stm32_lptim_cnt *const priv = counter->priv;
|
|
|
|
return stm32_lptim_cnt_get_ceiling(priv, buf);
|
|
}
|
|
|
|
static ssize_t stm32_lptim_cnt_ceiling_write(struct counter_device *counter,
|
|
struct counter_count *count,
|
|
void *private,
|
|
const char *buf, size_t len)
|
|
{
|
|
struct stm32_lptim_cnt *const priv = counter->priv;
|
|
|
|
return stm32_lptim_cnt_set_ceiling(priv, buf, len);
|
|
}
|
|
|
|
static const struct counter_count_ext stm32_lptim_cnt_ext[] = {
|
|
{
|
|
.name = "enable",
|
|
.read = stm32_lptim_cnt_enable_read,
|
|
.write = stm32_lptim_cnt_enable_write
|
|
},
|
|
{
|
|
.name = "ceiling",
|
|
.read = stm32_lptim_cnt_ceiling_read,
|
|
.write = stm32_lptim_cnt_ceiling_write
|
|
},
|
|
};
|
|
|
|
static int stm32_lptim_cnt_action_get(struct counter_device *counter,
|
|
struct counter_count *count,
|
|
struct counter_synapse *synapse,
|
|
size_t *action)
|
|
{
|
|
struct stm32_lptim_cnt *const priv = counter->priv;
|
|
size_t function;
|
|
int err;
|
|
|
|
err = stm32_lptim_cnt_function_get(counter, count, &function);
|
|
if (err)
|
|
return err;
|
|
|
|
switch (function) {
|
|
case STM32_LPTIM_COUNTER_INCREASE:
|
|
/* LP Timer acts as up-counter on input 1 */
|
|
if (synapse->signal->id == count->synapses[0].signal->id)
|
|
*action = priv->polarity;
|
|
else
|
|
*action = STM32_LPTIM_SYNAPSE_ACTION_NONE;
|
|
return 0;
|
|
case STM32_LPTIM_ENCODER_BOTH_EDGE:
|
|
*action = priv->polarity;
|
|
return 0;
|
|
}
|
|
|
|
return -EINVAL;
|
|
}
|
|
|
|
static int stm32_lptim_cnt_action_set(struct counter_device *counter,
|
|
struct counter_count *count,
|
|
struct counter_synapse *synapse,
|
|
size_t action)
|
|
{
|
|
struct stm32_lptim_cnt *const priv = counter->priv;
|
|
size_t function;
|
|
int err;
|
|
|
|
if (stm32_lptim_is_enabled(priv))
|
|
return -EBUSY;
|
|
|
|
err = stm32_lptim_cnt_function_get(counter, count, &function);
|
|
if (err)
|
|
return err;
|
|
|
|
/* only set polarity when in counter mode (on input 1) */
|
|
if (function == STM32_LPTIM_COUNTER_INCREASE
|
|
&& synapse->signal->id == count->synapses[0].signal->id) {
|
|
switch (action) {
|
|
case STM32_LPTIM_SYNAPSE_ACTION_RISING_EDGE:
|
|
case STM32_LPTIM_SYNAPSE_ACTION_FALLING_EDGE:
|
|
case STM32_LPTIM_SYNAPSE_ACTION_BOTH_EDGES:
|
|
priv->polarity = action;
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
return -EINVAL;
|
|
}
|
|
|
|
static const struct counter_ops stm32_lptim_cnt_ops = {
|
|
.count_read = stm32_lptim_cnt_read,
|
|
.function_get = stm32_lptim_cnt_function_get,
|
|
.function_set = stm32_lptim_cnt_function_set,
|
|
.action_get = stm32_lptim_cnt_action_get,
|
|
.action_set = stm32_lptim_cnt_action_set,
|
|
};
|
|
|
|
static struct counter_signal stm32_lptim_cnt_signals[] = {
|
|
{
|
|
.id = 0,
|
|
.name = "Channel 1 Quadrature A"
|
|
},
|
|
{
|
|
.id = 1,
|
|
.name = "Channel 1 Quadrature B"
|
|
}
|
|
};
|
|
|
|
static struct counter_synapse stm32_lptim_cnt_synapses[] = {
|
|
{
|
|
.actions_list = stm32_lptim_cnt_synapse_actions,
|
|
.num_actions = ARRAY_SIZE(stm32_lptim_cnt_synapse_actions),
|
|
.signal = &stm32_lptim_cnt_signals[0]
|
|
},
|
|
{
|
|
.actions_list = stm32_lptim_cnt_synapse_actions,
|
|
.num_actions = ARRAY_SIZE(stm32_lptim_cnt_synapse_actions),
|
|
.signal = &stm32_lptim_cnt_signals[1]
|
|
}
|
|
};
|
|
|
|
/* LP timer with encoder */
|
|
static struct counter_count stm32_lptim_enc_counts = {
|
|
.id = 0,
|
|
.name = "LPTimer Count",
|
|
.functions_list = stm32_lptim_cnt_functions,
|
|
.num_functions = ARRAY_SIZE(stm32_lptim_cnt_functions),
|
|
.synapses = stm32_lptim_cnt_synapses,
|
|
.num_synapses = ARRAY_SIZE(stm32_lptim_cnt_synapses),
|
|
.ext = stm32_lptim_cnt_ext,
|
|
.num_ext = ARRAY_SIZE(stm32_lptim_cnt_ext)
|
|
};
|
|
|
|
/* LP timer without encoder (counter only) */
|
|
static struct counter_count stm32_lptim_in1_counts = {
|
|
.id = 0,
|
|
.name = "LPTimer Count",
|
|
.functions_list = stm32_lptim_cnt_functions,
|
|
.num_functions = 1,
|
|
.synapses = stm32_lptim_cnt_synapses,
|
|
.num_synapses = 1,
|
|
.ext = stm32_lptim_cnt_ext,
|
|
.num_ext = ARRAY_SIZE(stm32_lptim_cnt_ext)
|
|
};
|
|
|
|
static int stm32_lptim_cnt_probe(struct platform_device *pdev)
|
|
{
|
|
struct stm32_lptimer *ddata = dev_get_drvdata(pdev->dev.parent);
|
|
struct stm32_lptim_cnt *priv;
|
|
struct iio_dev *indio_dev;
|
|
int ret;
|
|
|
|
if (IS_ERR_OR_NULL(ddata))
|
|
return -EINVAL;
|
|
|
|
indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*priv));
|
|
if (!indio_dev)
|
|
return -ENOMEM;
|
|
|
|
priv = iio_priv(indio_dev);
|
|
priv->dev = &pdev->dev;
|
|
priv->regmap = ddata->regmap;
|
|
priv->clk = ddata->clk;
|
|
priv->ceiling = STM32_LPTIM_MAX_ARR;
|
|
|
|
/* Initialize IIO device */
|
|
indio_dev->name = dev_name(&pdev->dev);
|
|
indio_dev->dev.parent = &pdev->dev;
|
|
indio_dev->dev.of_node = pdev->dev.of_node;
|
|
indio_dev->info = &stm32_lptim_cnt_iio_info;
|
|
if (ddata->has_encoder)
|
|
indio_dev->channels = &stm32_lptim_enc_channels;
|
|
else
|
|
indio_dev->channels = &stm32_lptim_cnt_channels;
|
|
indio_dev->num_channels = 1;
|
|
|
|
/* Initialize Counter device */
|
|
priv->counter.name = dev_name(&pdev->dev);
|
|
priv->counter.parent = &pdev->dev;
|
|
priv->counter.ops = &stm32_lptim_cnt_ops;
|
|
if (ddata->has_encoder) {
|
|
priv->counter.counts = &stm32_lptim_enc_counts;
|
|
priv->counter.num_signals = ARRAY_SIZE(stm32_lptim_cnt_signals);
|
|
} else {
|
|
priv->counter.counts = &stm32_lptim_in1_counts;
|
|
priv->counter.num_signals = 1;
|
|
}
|
|
priv->counter.num_counts = 1;
|
|
priv->counter.signals = stm32_lptim_cnt_signals;
|
|
priv->counter.priv = priv;
|
|
|
|
platform_set_drvdata(pdev, priv);
|
|
|
|
ret = devm_iio_device_register(&pdev->dev, indio_dev);
|
|
if (ret)
|
|
return ret;
|
|
|
|
return devm_counter_register(&pdev->dev, &priv->counter);
|
|
}
|
|
|
|
#ifdef CONFIG_PM_SLEEP
|
|
static int stm32_lptim_cnt_suspend(struct device *dev)
|
|
{
|
|
struct stm32_lptim_cnt *priv = dev_get_drvdata(dev);
|
|
int ret;
|
|
|
|
/* Only take care of enabled counter: don't disturb other MFD child */
|
|
if (priv->enabled) {
|
|
ret = stm32_lptim_setup(priv, 0);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = stm32_lptim_set_enable_state(priv, 0);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* Force enable state for later resume */
|
|
priv->enabled = true;
|
|
}
|
|
|
|
return pinctrl_pm_select_sleep_state(dev);
|
|
}
|
|
|
|
static int stm32_lptim_cnt_resume(struct device *dev)
|
|
{
|
|
struct stm32_lptim_cnt *priv = dev_get_drvdata(dev);
|
|
int ret;
|
|
|
|
ret = pinctrl_pm_select_default_state(dev);
|
|
if (ret)
|
|
return ret;
|
|
|
|
if (priv->enabled) {
|
|
priv->enabled = false;
|
|
ret = stm32_lptim_setup(priv, 1);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = stm32_lptim_set_enable_state(priv, 1);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
static SIMPLE_DEV_PM_OPS(stm32_lptim_cnt_pm_ops, stm32_lptim_cnt_suspend,
|
|
stm32_lptim_cnt_resume);
|
|
|
|
static const struct of_device_id stm32_lptim_cnt_of_match[] = {
|
|
{ .compatible = "st,stm32-lptimer-counter", },
|
|
{},
|
|
};
|
|
MODULE_DEVICE_TABLE(of, stm32_lptim_cnt_of_match);
|
|
|
|
static struct platform_driver stm32_lptim_cnt_driver = {
|
|
.probe = stm32_lptim_cnt_probe,
|
|
.driver = {
|
|
.name = "stm32-lptimer-counter",
|
|
.of_match_table = stm32_lptim_cnt_of_match,
|
|
.pm = &stm32_lptim_cnt_pm_ops,
|
|
},
|
|
};
|
|
module_platform_driver(stm32_lptim_cnt_driver);
|
|
|
|
MODULE_AUTHOR("Fabrice Gasnier <fabrice.gasnier@st.com>");
|
|
MODULE_ALIAS("platform:stm32-lptimer-counter");
|
|
MODULE_DESCRIPTION("STMicroelectronics STM32 LPTIM counter driver");
|
|
MODULE_LICENSE("GPL v2");
|