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f357439229
The register map used for 'cbf_pll' is the same as the one defined for the CLK_ALPHA_PLL_TYPE_HUAYRA_APSS indice in the 'clk_alpha_pll_regs' array. Drop the local register map and use the global one instead to reduce code duplication. No functional changes intended. Compile tested only. Suggested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Gabor Juhos <j4g8y7@gmail.com> Link: https://lore.kernel.org/r/20240328-apss-ipq-pll-cleanup-v4-5-eddbf617f0c8@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
367 lines
9.3 KiB
C
367 lines
9.3 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2022, 2023 Linaro Ltd.
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*/
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#include <linux/bitfield.h>
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/interconnect-clk.h>
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#include <linux/interconnect-provider.h>
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#include <linux/of.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <dt-bindings/interconnect/qcom,msm8996-cbf.h>
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#include "clk-alpha-pll.h"
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#include "clk-regmap.h"
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/* Need to match the order of clocks in DT binding */
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enum {
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DT_XO,
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DT_APCS_AUX,
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};
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enum {
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CBF_XO_INDEX,
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CBF_PLL_INDEX,
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CBF_DIV_INDEX,
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CBF_APCS_AUX_INDEX,
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};
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#define DIV_THRESHOLD 600000000
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#define CBF_MUX_OFFSET 0x18
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#define CBF_MUX_PARENT_MASK GENMASK(1, 0)
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#define CBF_MUX_AUTO_CLK_SEL_ALWAYS_ON_MASK GENMASK(5, 4)
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#define CBF_MUX_AUTO_CLK_SEL_ALWAYS_ON_GPLL0_SEL \
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FIELD_PREP(CBF_MUX_AUTO_CLK_SEL_ALWAYS_ON_MASK, 0x03)
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#define CBF_MUX_AUTO_CLK_SEL_BIT BIT(6)
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#define CBF_PLL_OFFSET 0xf000
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static struct alpha_pll_config cbfpll_config = {
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.l = 72,
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.config_ctl_val = 0x200d4828,
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.config_ctl_hi_val = 0x006,
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.test_ctl_val = 0x1c000000,
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.test_ctl_hi_val = 0x00004000,
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.pre_div_mask = BIT(12),
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.post_div_mask = 0x3 << 8,
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.post_div_val = 0x1 << 8,
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.main_output_mask = BIT(0),
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.early_output_mask = BIT(3),
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};
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static struct clk_alpha_pll cbf_pll = {
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.offset = CBF_PLL_OFFSET,
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_HUAYRA_APSS],
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.flags = SUPPORTS_DYNAMIC_UPDATE | SUPPORTS_FSM_MODE,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "cbf_pll",
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.parent_data = (const struct clk_parent_data[]) {
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{ .index = DT_XO, },
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},
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.num_parents = 1,
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.ops = &clk_alpha_pll_hwfsm_ops,
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},
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};
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static struct clk_fixed_factor cbf_pll_postdiv = {
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.mult = 1,
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.div = 2,
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.hw.init = &(struct clk_init_data){
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.name = "cbf_pll_postdiv",
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.parent_hws = (const struct clk_hw*[]){
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&cbf_pll.clkr.hw
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},
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.num_parents = 1,
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.ops = &clk_fixed_factor_ops,
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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static const struct clk_parent_data cbf_mux_parent_data[] = {
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{ .index = DT_XO },
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{ .hw = &cbf_pll.clkr.hw },
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{ .hw = &cbf_pll_postdiv.hw },
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{ .index = DT_APCS_AUX },
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};
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struct clk_cbf_8996_mux {
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u32 reg;
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struct notifier_block nb;
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struct clk_regmap clkr;
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};
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static struct clk_cbf_8996_mux *to_clk_cbf_8996_mux(struct clk_regmap *clkr)
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{
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return container_of(clkr, struct clk_cbf_8996_mux, clkr);
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}
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static int cbf_clk_notifier_cb(struct notifier_block *nb, unsigned long event,
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void *data);
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static u8 clk_cbf_8996_mux_get_parent(struct clk_hw *hw)
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{
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struct clk_regmap *clkr = to_clk_regmap(hw);
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struct clk_cbf_8996_mux *mux = to_clk_cbf_8996_mux(clkr);
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u32 val;
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regmap_read(clkr->regmap, mux->reg, &val);
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return FIELD_GET(CBF_MUX_PARENT_MASK, val);
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}
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static int clk_cbf_8996_mux_set_parent(struct clk_hw *hw, u8 index)
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{
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struct clk_regmap *clkr = to_clk_regmap(hw);
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struct clk_cbf_8996_mux *mux = to_clk_cbf_8996_mux(clkr);
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u32 val;
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val = FIELD_PREP(CBF_MUX_PARENT_MASK, index);
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return regmap_update_bits(clkr->regmap, mux->reg, CBF_MUX_PARENT_MASK, val);
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}
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static int clk_cbf_8996_mux_determine_rate(struct clk_hw *hw,
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struct clk_rate_request *req)
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{
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struct clk_hw *parent;
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if (req->rate < (DIV_THRESHOLD / cbf_pll_postdiv.div))
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return -EINVAL;
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if (req->rate < DIV_THRESHOLD)
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parent = clk_hw_get_parent_by_index(hw, CBF_DIV_INDEX);
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else
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parent = clk_hw_get_parent_by_index(hw, CBF_PLL_INDEX);
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if (!parent)
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return -EINVAL;
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req->best_parent_rate = clk_hw_round_rate(parent, req->rate);
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req->best_parent_hw = parent;
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return 0;
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}
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static const struct clk_ops clk_cbf_8996_mux_ops = {
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.set_parent = clk_cbf_8996_mux_set_parent,
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.get_parent = clk_cbf_8996_mux_get_parent,
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.determine_rate = clk_cbf_8996_mux_determine_rate,
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};
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static struct clk_cbf_8996_mux cbf_mux = {
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.reg = CBF_MUX_OFFSET,
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.nb.notifier_call = cbf_clk_notifier_cb,
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.clkr.hw.init = &(struct clk_init_data) {
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.name = "cbf_mux",
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.parent_data = cbf_mux_parent_data,
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.num_parents = ARRAY_SIZE(cbf_mux_parent_data),
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.ops = &clk_cbf_8996_mux_ops,
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/* CPU clock is critical and should never be gated */
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.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
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},
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};
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static int cbf_clk_notifier_cb(struct notifier_block *nb, unsigned long event,
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void *data)
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{
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struct clk_notifier_data *cnd = data;
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switch (event) {
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case PRE_RATE_CHANGE:
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/*
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* Avoid overvolting. clk_core_set_rate_nolock() walks from top
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* to bottom, so it will change the rate of the PLL before
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* chaging the parent of PMUX. This can result in pmux getting
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* clocked twice the expected rate.
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*
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* Manually switch to PLL/2 here.
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*/
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if (cnd->old_rate > DIV_THRESHOLD &&
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cnd->new_rate < DIV_THRESHOLD)
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clk_cbf_8996_mux_set_parent(&cbf_mux.clkr.hw, CBF_DIV_INDEX);
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break;
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case ABORT_RATE_CHANGE:
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/* Revert manual change */
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if (cnd->new_rate < DIV_THRESHOLD &&
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cnd->old_rate > DIV_THRESHOLD)
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clk_cbf_8996_mux_set_parent(&cbf_mux.clkr.hw, CBF_PLL_INDEX);
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break;
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default:
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break;
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}
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return notifier_from_errno(0);
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};
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static struct clk_hw *cbf_msm8996_hw_clks[] = {
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&cbf_pll_postdiv.hw,
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};
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static struct clk_regmap *cbf_msm8996_clks[] = {
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&cbf_pll.clkr,
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&cbf_mux.clkr,
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};
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static const struct regmap_config cbf_msm8996_regmap_config = {
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.reg_bits = 32,
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.reg_stride = 4,
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.val_bits = 32,
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.max_register = 0x10000,
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.fast_io = true,
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.val_format_endian = REGMAP_ENDIAN_LITTLE,
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};
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#ifdef CONFIG_INTERCONNECT
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/* Random ID that doesn't clash with main qnoc and OSM */
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#define CBF_MASTER_NODE 2000
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static int qcom_msm8996_cbf_icc_register(struct platform_device *pdev, struct clk_hw *cbf_hw)
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{
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struct device *dev = &pdev->dev;
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struct clk *clk = devm_clk_hw_get_clk(dev, cbf_hw, "cbf");
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const struct icc_clk_data data[] = {
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{ .clk = clk, .name = "cbf", },
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};
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struct icc_provider *provider;
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provider = icc_clk_register(dev, CBF_MASTER_NODE, ARRAY_SIZE(data), data);
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if (IS_ERR(provider))
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return PTR_ERR(provider);
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platform_set_drvdata(pdev, provider);
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return 0;
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}
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static void qcom_msm8996_cbf_icc_remove(struct platform_device *pdev)
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{
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struct icc_provider *provider = platform_get_drvdata(pdev);
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icc_clk_unregister(provider);
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}
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#define qcom_msm8996_cbf_icc_sync_state icc_sync_state
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#else
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static int qcom_msm8996_cbf_icc_register(struct platform_device *pdev, struct clk_hw *cbf_hw)
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{
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dev_warn(&pdev->dev, "CONFIG_INTERCONNECT is disabled, CBF clock is fixed\n");
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return 0;
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}
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#define qcom_msm8996_cbf_icc_remove(pdev) { }
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#define qcom_msm8996_cbf_icc_sync_state NULL
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#endif
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static int qcom_msm8996_cbf_probe(struct platform_device *pdev)
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{
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void __iomem *base;
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struct regmap *regmap;
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struct device *dev = &pdev->dev;
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int i, ret;
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base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(base))
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return PTR_ERR(base);
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regmap = devm_regmap_init_mmio(dev, base, &cbf_msm8996_regmap_config);
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if (IS_ERR(regmap))
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return PTR_ERR(regmap);
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/* Select GPLL0 for 300MHz for the CBF clock */
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regmap_write(regmap, CBF_MUX_OFFSET, 0x3);
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/* Ensure write goes through before PLLs are reconfigured */
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udelay(5);
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/* Set the auto clock sel always-on source to GPLL0/2 (300MHz) */
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regmap_update_bits(regmap, CBF_MUX_OFFSET,
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CBF_MUX_AUTO_CLK_SEL_ALWAYS_ON_MASK,
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CBF_MUX_AUTO_CLK_SEL_ALWAYS_ON_GPLL0_SEL);
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clk_alpha_pll_configure(&cbf_pll, regmap, &cbfpll_config);
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/* Wait for PLL(s) to lock */
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udelay(50);
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/* Enable auto clock selection for CBF */
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regmap_update_bits(regmap, CBF_MUX_OFFSET,
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CBF_MUX_AUTO_CLK_SEL_BIT,
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CBF_MUX_AUTO_CLK_SEL_BIT);
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/* Ensure write goes through before muxes are switched */
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udelay(5);
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/* Switch CBF to use the primary PLL */
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regmap_update_bits(regmap, CBF_MUX_OFFSET, CBF_MUX_PARENT_MASK, 0x1);
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if (of_device_is_compatible(dev->of_node, "qcom,msm8996pro-cbf")) {
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cbfpll_config.post_div_val = 0x3 << 8;
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cbf_pll_postdiv.div = 4;
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}
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for (i = 0; i < ARRAY_SIZE(cbf_msm8996_hw_clks); i++) {
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ret = devm_clk_hw_register(dev, cbf_msm8996_hw_clks[i]);
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if (ret)
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return ret;
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}
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for (i = 0; i < ARRAY_SIZE(cbf_msm8996_clks); i++) {
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ret = devm_clk_register_regmap(dev, cbf_msm8996_clks[i]);
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if (ret)
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return ret;
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}
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ret = devm_clk_notifier_register(dev, cbf_mux.clkr.hw.clk, &cbf_mux.nb);
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if (ret)
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return ret;
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ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, &cbf_mux.clkr.hw);
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if (ret)
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return ret;
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return qcom_msm8996_cbf_icc_register(pdev, &cbf_mux.clkr.hw);
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}
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static void qcom_msm8996_cbf_remove(struct platform_device *pdev)
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{
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qcom_msm8996_cbf_icc_remove(pdev);
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}
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static const struct of_device_id qcom_msm8996_cbf_match_table[] = {
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{ .compatible = "qcom,msm8996-cbf" },
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{ .compatible = "qcom,msm8996pro-cbf" },
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{ /* sentinel */ },
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};
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MODULE_DEVICE_TABLE(of, qcom_msm8996_cbf_match_table);
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static struct platform_driver qcom_msm8996_cbf_driver = {
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.probe = qcom_msm8996_cbf_probe,
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.remove_new = qcom_msm8996_cbf_remove,
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.driver = {
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.name = "qcom-msm8996-cbf",
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.of_match_table = qcom_msm8996_cbf_match_table,
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.sync_state = qcom_msm8996_cbf_icc_sync_state,
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},
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};
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/* Register early enough to fix the clock to be used for other cores */
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static int __init qcom_msm8996_cbf_init(void)
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{
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return platform_driver_register(&qcom_msm8996_cbf_driver);
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}
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postcore_initcall(qcom_msm8996_cbf_init);
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static void __exit qcom_msm8996_cbf_exit(void)
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{
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platform_driver_unregister(&qcom_msm8996_cbf_driver);
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}
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module_exit(qcom_msm8996_cbf_exit);
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MODULE_DESCRIPTION("QCOM MSM8996 CPU Bus Fabric Clock Driver");
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MODULE_LICENSE("GPL");
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