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c46a74ff05
FTDI FT2232H is a USB to GPIO chip. Sealevel produces some devices with this chip. FT2232H presents itself as a composite device with two interfaces (each is an "MPSSE"). Each MPSSE has two banks (high and low) of 8 GPIO each. I believe some MPSSE's have only one bank, but I don't know how to identify them (I don't have any for testing) and as a result are unsupported for the time being. Additionally, this driver provides software polling-based interrupts for edge detection. For the Sealevel device I have to test with, this works well because there is hardware debouncing. From talking to Sealevel's people, this is their preferred way to do edge detection. Signed-off-by: Mary Strodl <mstrodl@csh.rit.edu> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20241009131131.1618329-1-mstrodl@csh.rit.edu Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
523 lines
13 KiB
C
523 lines
13 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* FTDI MPSSE GPIO support
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*
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* Based on code by Anatolij Gustschin
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*
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* Copyright (C) 2024 Mary Strodl <mstrodl@csh.rit.edu>
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*/
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#include <linux/cleanup.h>
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#include <linux/gpio/driver.h>
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#include <linux/mutex.h>
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#include <linux/usb.h>
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struct mpsse_priv {
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struct gpio_chip gpio;
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struct usb_device *udev; /* USB device encompassing all MPSSEs */
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struct usb_interface *intf; /* USB interface for this MPSSE */
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u8 intf_id; /* USB interface number for this MPSSE */
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struct work_struct irq_work; /* polling work thread */
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struct mutex irq_mutex; /* lock over irq_data */
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atomic_t irq_type[16]; /* pin -> edge detection type */
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atomic_t irq_enabled;
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int id;
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u8 gpio_outputs[2]; /* Output states for GPIOs [L, H] */
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u8 gpio_dir[2]; /* Directions for GPIOs [L, H] */
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u8 *bulk_in_buf; /* Extra recv buffer to grab status bytes */
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struct usb_endpoint_descriptor *bulk_in;
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struct usb_endpoint_descriptor *bulk_out;
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struct mutex io_mutex; /* sync I/O with disconnect */
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};
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struct bulk_desc {
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bool tx; /* direction of bulk transfer */
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u8 *data; /* input (tx) or output (rx) */
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int len; /* Length of `data` if tx, or length of */
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/* Data to read if rx */
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int len_actual; /* Length successfully transferred */
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int timeout;
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};
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static const struct usb_device_id gpio_mpsse_table[] = {
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{ USB_DEVICE(0x0c52, 0xa064) }, /* SeaLevel Systems, Inc. */
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{ } /* Terminating entry */
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};
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MODULE_DEVICE_TABLE(usb, gpio_mpsse_table);
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static DEFINE_IDA(gpio_mpsse_ida);
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/* MPSSE commands */
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#define SET_BITS_CMD 0x80
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#define GET_BITS_CMD 0x81
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#define SET_BITMODE_REQUEST 0x0B
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#define MODE_MPSSE (2 << 8)
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#define MODE_RESET 0
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/* Arbitrarily decided. This could probably be much less */
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#define MPSSE_WRITE_TIMEOUT 5000
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#define MPSSE_READ_TIMEOUT 5000
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/* 1 millisecond, also pretty arbitrary */
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#define MPSSE_POLL_INTERVAL 1000
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static int mpsse_bulk_xfer(struct usb_interface *intf, struct bulk_desc *desc)
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{
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struct mpsse_priv *priv = usb_get_intfdata(intf);
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struct usb_device *udev = priv->udev;
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unsigned int pipe;
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int ret;
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if (desc->tx)
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pipe = usb_sndbulkpipe(udev, priv->bulk_out->bEndpointAddress);
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else
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pipe = usb_rcvbulkpipe(udev, priv->bulk_in->bEndpointAddress);
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ret = usb_bulk_msg(udev, pipe, desc->data, desc->len,
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&desc->len_actual, desc->timeout);
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if (ret)
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dev_dbg(&udev->dev, "mpsse: bulk transfer failed: %d\n", ret);
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return ret;
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}
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static int mpsse_write(struct usb_interface *intf,
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u8 *buf, size_t len)
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{
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int ret;
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struct bulk_desc desc;
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desc.len_actual = 0;
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desc.tx = true;
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desc.data = buf;
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desc.len = len;
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desc.timeout = MPSSE_WRITE_TIMEOUT;
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ret = mpsse_bulk_xfer(intf, &desc);
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return ret;
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}
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static int mpsse_read(struct usb_interface *intf, u8 *buf, size_t len)
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{
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int ret;
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struct bulk_desc desc;
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struct mpsse_priv *priv = usb_get_intfdata(intf);
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desc.len_actual = 0;
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desc.tx = false;
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desc.data = priv->bulk_in_buf;
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/* Device sends 2 additional status bytes, read len + 2 */
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desc.len = min_t(size_t, len + 2, usb_endpoint_maxp(priv->bulk_in));
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desc.timeout = MPSSE_READ_TIMEOUT;
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ret = mpsse_bulk_xfer(intf, &desc);
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if (ret)
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return ret;
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/* Did we get enough data? */
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if (desc.len_actual < desc.len)
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return -EIO;
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memcpy(buf, desc.data + 2, desc.len_actual - 2);
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return ret;
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}
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static int gpio_mpsse_set_bank(struct mpsse_priv *priv, u8 bank)
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{
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int ret;
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u8 tx_buf[3] = {
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SET_BITS_CMD | (bank << 1),
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priv->gpio_outputs[bank],
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priv->gpio_dir[bank],
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};
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ret = mpsse_write(priv->intf, tx_buf, 3);
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return ret;
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}
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static int gpio_mpsse_get_bank(struct mpsse_priv *priv, u8 bank)
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{
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int ret;
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u8 buf = GET_BITS_CMD | (bank << 1);
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ret = mpsse_write(priv->intf, &buf, 1);
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if (ret)
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return ret;
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ret = mpsse_read(priv->intf, &buf, 1);
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if (ret)
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return ret;
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return buf;
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}
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static void gpio_mpsse_set_multiple(struct gpio_chip *chip, unsigned long *mask,
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unsigned long *bits)
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{
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unsigned long i, bank, bank_mask, bank_bits;
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int ret;
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struct mpsse_priv *priv = gpiochip_get_data(chip);
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guard(mutex)(&priv->io_mutex);
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for_each_set_clump8(i, bank_mask, mask, chip->ngpio) {
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bank = i / 8;
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if (bank_mask) {
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bank_bits = bitmap_get_value8(bits, i);
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/* Zero out pins we want to change */
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priv->gpio_outputs[bank] &= ~bank_mask;
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/* Set pins we care about */
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priv->gpio_outputs[bank] |= bank_bits & bank_mask;
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ret = gpio_mpsse_set_bank(priv, bank);
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if (ret)
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dev_err(&priv->intf->dev,
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"Couldn't set values for bank %ld!",
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bank);
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}
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}
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}
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static int gpio_mpsse_get_multiple(struct gpio_chip *chip, unsigned long *mask,
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unsigned long *bits)
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{
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unsigned long i, bank, bank_mask;
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int ret;
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struct mpsse_priv *priv = gpiochip_get_data(chip);
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guard(mutex)(&priv->io_mutex);
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for_each_set_clump8(i, bank_mask, mask, chip->ngpio) {
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bank = i / 8;
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if (bank_mask) {
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ret = gpio_mpsse_get_bank(priv, bank);
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if (ret < 0)
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return ret;
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bitmap_set_value8(bits, ret & bank_mask, i);
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}
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}
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return 0;
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}
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static int gpio_mpsse_gpio_get(struct gpio_chip *chip, unsigned int offset)
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{
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int err;
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unsigned long mask = 0, bits = 0;
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__set_bit(offset, &mask);
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err = gpio_mpsse_get_multiple(chip, &mask, &bits);
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if (err)
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return err;
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/* == is not guaranteed to give 1 if true */
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if (bits)
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return 1;
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else
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return 0;
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}
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static void gpio_mpsse_gpio_set(struct gpio_chip *chip, unsigned int offset,
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int value)
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{
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unsigned long mask = 0, bits = 0;
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__set_bit(offset, &mask);
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if (value)
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__set_bit(offset, &bits);
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gpio_mpsse_set_multiple(chip, &mask, &bits);
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}
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static int gpio_mpsse_direction_output(struct gpio_chip *chip,
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unsigned int offset, int value)
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{
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struct mpsse_priv *priv = gpiochip_get_data(chip);
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int bank = (offset & 8) >> 3;
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int bank_offset = offset & 7;
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scoped_guard(mutex, &priv->io_mutex)
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priv->gpio_dir[bank] |= BIT(bank_offset);
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gpio_mpsse_gpio_set(chip, offset, value);
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return 0;
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}
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static int gpio_mpsse_direction_input(struct gpio_chip *chip,
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unsigned int offset)
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{
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struct mpsse_priv *priv = gpiochip_get_data(chip);
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int bank = (offset & 8) >> 3;
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int bank_offset = offset & 7;
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guard(mutex)(&priv->io_mutex);
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priv->gpio_dir[bank] &= ~BIT(bank_offset);
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gpio_mpsse_set_bank(priv, bank);
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return 0;
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}
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static int gpio_mpsse_get_direction(struct gpio_chip *chip,
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unsigned int offset)
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{
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int ret;
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int bank = (offset & 8) >> 3;
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int bank_offset = offset & 7;
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struct mpsse_priv *priv = gpiochip_get_data(chip);
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guard(mutex)(&priv->io_mutex);
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/* MPSSE directions are inverted */
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if (priv->gpio_dir[bank] & BIT(bank_offset))
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ret = GPIO_LINE_DIRECTION_OUT;
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else
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ret = GPIO_LINE_DIRECTION_IN;
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return ret;
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}
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static void gpio_mpsse_poll(struct work_struct *work)
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{
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unsigned long pin_mask, pin_states, flags;
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int irq_enabled, offset, err, value, fire_irq,
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irq, old_value[16], irq_type[16];
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struct mpsse_priv *priv = container_of(work, struct mpsse_priv,
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irq_work);
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for (offset = 0; offset < priv->gpio.ngpio; ++offset)
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old_value[offset] = -1;
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while ((irq_enabled = atomic_read(&priv->irq_enabled))) {
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usleep_range(MPSSE_POLL_INTERVAL, MPSSE_POLL_INTERVAL + 1000);
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/* Cleanup will trigger at the end of the loop */
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guard(mutex)(&priv->irq_mutex);
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pin_mask = 0;
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pin_states = 0;
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for (offset = 0; offset < priv->gpio.ngpio; ++offset) {
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irq_type[offset] = atomic_read(&priv->irq_type[offset]);
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if (irq_type[offset] != IRQ_TYPE_NONE &&
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irq_enabled & BIT(offset))
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pin_mask |= BIT(offset);
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else
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old_value[offset] = -1;
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}
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err = gpio_mpsse_get_multiple(&priv->gpio, &pin_mask,
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&pin_states);
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if (err) {
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dev_err_ratelimited(&priv->intf->dev,
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"Error polling!\n");
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continue;
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}
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/* Check each value */
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for (offset = 0; offset < priv->gpio.ngpio; ++offset) {
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if (old_value[offset] == -1)
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continue;
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fire_irq = 0;
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value = pin_states & BIT(offset);
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switch (irq_type[offset]) {
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case IRQ_TYPE_EDGE_RISING:
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fire_irq = value > old_value[offset];
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break;
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case IRQ_TYPE_EDGE_FALLING:
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fire_irq = value < old_value[offset];
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break;
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case IRQ_TYPE_EDGE_BOTH:
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fire_irq = value != old_value[offset];
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break;
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}
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if (!fire_irq)
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continue;
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irq = irq_find_mapping(priv->gpio.irq.domain,
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offset);
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local_irq_save(flags);
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generic_handle_irq(irq);
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local_irq_disable();
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local_irq_restore(flags);
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}
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/* Sync back values so we can refer to them next tick */
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for (offset = 0; offset < priv->gpio.ngpio; ++offset)
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if (irq_type[offset] != IRQ_TYPE_NONE &&
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irq_enabled & BIT(offset))
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old_value[offset] = pin_states & BIT(offset);
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}
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}
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static int gpio_mpsse_set_irq_type(struct irq_data *irqd, unsigned int type)
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{
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int offset;
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struct mpsse_priv *priv = irq_data_get_irq_chip_data(irqd);
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offset = irqd->hwirq;
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atomic_set(&priv->irq_type[offset], type & IRQ_TYPE_EDGE_BOTH);
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return 0;
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}
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static void gpio_mpsse_irq_disable(struct irq_data *irqd)
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{
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struct mpsse_priv *priv = irq_data_get_irq_chip_data(irqd);
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atomic_and(~BIT(irqd->hwirq), &priv->irq_enabled);
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gpiochip_disable_irq(&priv->gpio, irqd->hwirq);
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}
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static void gpio_mpsse_irq_enable(struct irq_data *irqd)
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{
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struct mpsse_priv *priv = irq_data_get_irq_chip_data(irqd);
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gpiochip_enable_irq(&priv->gpio, irqd->hwirq);
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/* If no-one else was using the IRQ, enable it */
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if (!atomic_fetch_or(BIT(irqd->hwirq), &priv->irq_enabled)) {
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INIT_WORK(&priv->irq_work, gpio_mpsse_poll);
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schedule_work(&priv->irq_work);
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}
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}
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static const struct irq_chip gpio_mpsse_irq_chip = {
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.name = "gpio-mpsse-irq",
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.irq_enable = gpio_mpsse_irq_enable,
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.irq_disable = gpio_mpsse_irq_disable,
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.irq_set_type = gpio_mpsse_set_irq_type,
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.flags = IRQCHIP_IMMUTABLE,
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GPIOCHIP_IRQ_RESOURCE_HELPERS,
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};
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static void gpio_mpsse_ida_remove(void *data)
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{
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struct mpsse_priv *priv = data;
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ida_simple_remove(&gpio_mpsse_ida, priv->id);
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}
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static int gpio_mpsse_probe(struct usb_interface *interface,
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const struct usb_device_id *id)
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{
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struct mpsse_priv *priv;
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struct device *dev;
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int err;
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dev = &interface->dev;
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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priv->udev = usb_get_dev(interface_to_usbdev(interface));
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priv->intf = interface;
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priv->intf_id = interface->cur_altsetting->desc.bInterfaceNumber;
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priv->id = ida_simple_get(&gpio_mpsse_ida, 0, 0, GFP_KERNEL);
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if (priv->id < 0)
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return priv->id;
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err = devm_add_action_or_reset(dev, gpio_mpsse_ida_remove, priv);
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if (err)
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return err;
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devm_mutex_init(dev, &priv->io_mutex);
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devm_mutex_init(dev, &priv->irq_mutex);
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priv->gpio.label = devm_kasprintf(dev, GFP_KERNEL,
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"gpio-mpsse.%d.%d",
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priv->id, priv->intf_id);
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if (!priv->gpio.label)
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return -ENOMEM;
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priv->gpio.owner = THIS_MODULE;
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priv->gpio.parent = interface->usb_dev;
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priv->gpio.get_direction = gpio_mpsse_get_direction;
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priv->gpio.direction_input = gpio_mpsse_direction_input;
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priv->gpio.direction_output = gpio_mpsse_direction_output;
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priv->gpio.get = gpio_mpsse_gpio_get;
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priv->gpio.set = gpio_mpsse_gpio_set;
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priv->gpio.get_multiple = gpio_mpsse_get_multiple;
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priv->gpio.set_multiple = gpio_mpsse_set_multiple;
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priv->gpio.base = -1;
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priv->gpio.ngpio = 16;
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priv->gpio.offset = priv->intf_id * priv->gpio.ngpio;
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priv->gpio.can_sleep = 1;
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err = usb_find_common_endpoints(interface->cur_altsetting,
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&priv->bulk_in, &priv->bulk_out,
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NULL, NULL);
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if (err)
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return err;
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priv->bulk_in_buf = devm_kmalloc(dev, usb_endpoint_maxp(priv->bulk_in),
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GFP_KERNEL);
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if (!priv->bulk_in_buf)
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return -ENOMEM;
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usb_set_intfdata(interface, priv);
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/* Reset mode, needed to correctly enter MPSSE mode */
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err = usb_control_msg(priv->udev, usb_sndctrlpipe(priv->udev, 0),
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SET_BITMODE_REQUEST,
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USB_TYPE_VENDOR | USB_RECIP_DEVICE | USB_DIR_OUT,
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MODE_RESET, priv->intf_id + 1, NULL, 0,
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USB_CTRL_SET_TIMEOUT);
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if (err)
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return err;
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/* Enter MPSSE mode */
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err = usb_control_msg(priv->udev, usb_sndctrlpipe(priv->udev, 0),
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SET_BITMODE_REQUEST,
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USB_TYPE_VENDOR | USB_RECIP_DEVICE | USB_DIR_OUT,
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MODE_MPSSE, priv->intf_id + 1, NULL, 0,
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USB_CTRL_SET_TIMEOUT);
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if (err)
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return err;
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gpio_irq_chip_set_chip(&priv->gpio.irq, &gpio_mpsse_irq_chip);
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priv->gpio.irq.parent_handler = NULL;
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priv->gpio.irq.num_parents = 0;
|
|
priv->gpio.irq.parents = NULL;
|
|
priv->gpio.irq.default_type = IRQ_TYPE_NONE;
|
|
priv->gpio.irq.handler = handle_simple_irq;
|
|
|
|
err = devm_gpiochip_add_data(dev, &priv->gpio, priv);
|
|
if (err)
|
|
return err;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void gpio_mpsse_disconnect(struct usb_interface *intf)
|
|
{
|
|
struct mpsse_priv *priv = usb_get_intfdata(intf);
|
|
|
|
priv->intf = NULL;
|
|
usb_set_intfdata(intf, NULL);
|
|
usb_put_dev(priv->udev);
|
|
}
|
|
|
|
static struct usb_driver gpio_mpsse_driver = {
|
|
.name = "gpio-mpsse",
|
|
.probe = gpio_mpsse_probe,
|
|
.disconnect = gpio_mpsse_disconnect,
|
|
.id_table = gpio_mpsse_table,
|
|
};
|
|
|
|
module_usb_driver(gpio_mpsse_driver);
|
|
|
|
MODULE_AUTHOR("Mary Strodl <mstrodl@csh.rit.edu>");
|
|
MODULE_DESCRIPTION("MPSSE GPIO driver");
|
|
MODULE_LICENSE("GPL");
|