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The clock-phase settings for the SDMMC controller in the SoCFPGA platforms reside in a register in the System Manager. Add a method to access that register through the syscon interface. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> Link: https://lore.kernel.org/r/20221114230217.202634-4-dinguyen@kernel.org Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
151 lines
4.0 KiB
C
151 lines
4.0 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Synopsys DesignWare Multimedia Card Interface driver
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*
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* Copyright (C) 2009 NXP Semiconductors
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* Copyright (C) 2009, 2010 Imagination Technologies Ltd.
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*/
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#include <linux/err.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/slab.h>
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#include <linux/mmc/host.h>
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#include <linux/mmc/mmc.h>
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#include <linux/of.h>
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#include <linux/mfd/altera-sysmgr.h>
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#include <linux/regmap.h>
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#include "dw_mmc.h"
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#include "dw_mmc-pltfm.h"
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#define SOCFPGA_DW_MMC_CLK_PHASE_STEP 45
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#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel, reg_shift) \
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((((smplsel) & 0x7) << reg_shift) | (((drvsel) & 0x7) << 0))
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int dw_mci_pltfm_register(struct platform_device *pdev,
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const struct dw_mci_drv_data *drv_data)
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{
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struct dw_mci *host;
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struct resource *regs;
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host = devm_kzalloc(&pdev->dev, sizeof(struct dw_mci), GFP_KERNEL);
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if (!host)
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return -ENOMEM;
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host->irq = platform_get_irq(pdev, 0);
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if (host->irq < 0)
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return host->irq;
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host->drv_data = drv_data;
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host->dev = &pdev->dev;
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host->irq_flags = 0;
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host->pdata = pdev->dev.platform_data;
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regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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host->regs = devm_ioremap_resource(&pdev->dev, regs);
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if (IS_ERR(host->regs))
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return PTR_ERR(host->regs);
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/* Get registers' physical base address */
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host->phy_regs = regs->start;
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platform_set_drvdata(pdev, host);
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return dw_mci_probe(host);
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}
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EXPORT_SYMBOL_GPL(dw_mci_pltfm_register);
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const struct dev_pm_ops dw_mci_pltfm_pmops = {
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SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
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pm_runtime_force_resume)
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SET_RUNTIME_PM_OPS(dw_mci_runtime_suspend,
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dw_mci_runtime_resume,
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NULL)
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};
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EXPORT_SYMBOL_GPL(dw_mci_pltfm_pmops);
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static int dw_mci_socfpga_priv_init(struct dw_mci *host)
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{
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struct device_node *np = host->dev->of_node;
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struct regmap *sys_mgr_base_addr;
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u32 clk_phase[2] = {0}, reg_offset, reg_shift;
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int i, rc, hs_timing;
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rc = of_property_read_variable_u32_array(np, "clk-phase-sd-hs", &clk_phase[0], 2, 0);
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if (rc < 0)
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return 0;
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sys_mgr_base_addr = altr_sysmgr_regmap_lookup_by_phandle(np, "altr,sysmgr-syscon");
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if (IS_ERR(sys_mgr_base_addr)) {
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dev_warn(host->dev, "clk-phase-sd-hs was specified, but failed to find altr,sys-mgr regmap!\n");
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return 0;
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}
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of_property_read_u32_index(np, "altr,sysmgr-syscon", 1, ®_offset);
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of_property_read_u32_index(np, "altr,sysmgr-syscon", 2, ®_shift);
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for (i = 0; i < ARRAY_SIZE(clk_phase); i++)
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clk_phase[i] /= SOCFPGA_DW_MMC_CLK_PHASE_STEP;
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hs_timing = SYSMGR_SDMMC_CTRL_SET(clk_phase[0], clk_phase[1], reg_shift);
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regmap_write(sys_mgr_base_addr, reg_offset, hs_timing);
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return 0;
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}
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static const struct dw_mci_drv_data socfpga_drv_data = {
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.init = dw_mci_socfpga_priv_init,
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};
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static const struct of_device_id dw_mci_pltfm_match[] = {
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{ .compatible = "snps,dw-mshc", },
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{ .compatible = "altr,socfpga-dw-mshc", .data = &socfpga_drv_data, },
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{ .compatible = "img,pistachio-dw-mshc", },
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{},
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};
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MODULE_DEVICE_TABLE(of, dw_mci_pltfm_match);
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static int dw_mci_pltfm_probe(struct platform_device *pdev)
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{
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const struct dw_mci_drv_data *drv_data = NULL;
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const struct of_device_id *match;
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if (pdev->dev.of_node) {
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match = of_match_node(dw_mci_pltfm_match, pdev->dev.of_node);
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drv_data = match->data;
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}
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return dw_mci_pltfm_register(pdev, drv_data);
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}
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int dw_mci_pltfm_remove(struct platform_device *pdev)
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{
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struct dw_mci *host = platform_get_drvdata(pdev);
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dw_mci_remove(host);
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return 0;
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}
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EXPORT_SYMBOL_GPL(dw_mci_pltfm_remove);
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static struct platform_driver dw_mci_pltfm_driver = {
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.probe = dw_mci_pltfm_probe,
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.remove = dw_mci_pltfm_remove,
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.driver = {
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.name = "dw_mmc",
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.probe_type = PROBE_PREFER_ASYNCHRONOUS,
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.of_match_table = dw_mci_pltfm_match,
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.pm = &dw_mci_pltfm_pmops,
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},
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};
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module_platform_driver(dw_mci_pltfm_driver);
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MODULE_DESCRIPTION("DW Multimedia Card Interface driver");
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MODULE_AUTHOR("NXP Semiconductor VietNam");
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MODULE_AUTHOR("Imagination Technologies Ltd");
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MODULE_LICENSE("GPL v2");
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