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07190a08ee
The Geode can safely use the TSC for highres, since: 1) Does not support frequency scaling, 2) The TSC _does_ count when the CPU is halted. Furthermore, the Geode supports a mode called "suspension on halt", where Suspend mode (which interacts with the power management states) is entered. TSC counting during suspend mode is controlled by bit 8 of the Bus Controller Configuration Register #0 (thanks Tom!). 3) no SMP :) Check if "RTSC counts during suspension" and remove the requirement for verification, so the clocksource code can safely select it as an timesource for the highres timers subsystem. Signed-off-by: Marcelo Tosatti <marcelo@kvack.org> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Ingo Molnar <mingo@elte.hu> Cc: john stultz <johnstul@us.ibm.com> Cc: Roman Zippel <zippel@linux-m68k.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
314 lines
9.0 KiB
C
314 lines
9.0 KiB
C
#ifndef __ASM_MSR_H
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#define __ASM_MSR_H
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#ifdef CONFIG_PARAVIRT
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#include <asm/paravirt.h>
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#else
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/*
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* Access to machine-specific registers (available on 586 and better only)
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* Note: the rd* operations modify the parameters directly (without using
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* pointer indirection), this allows gcc to optimize better
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*/
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#define rdmsr(msr,val1,val2) \
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__asm__ __volatile__("rdmsr" \
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: "=a" (val1), "=d" (val2) \
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: "c" (msr))
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#define wrmsr(msr,val1,val2) \
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__asm__ __volatile__("wrmsr" \
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: /* no outputs */ \
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: "c" (msr), "a" (val1), "d" (val2))
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#define rdmsrl(msr,val) do { \
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unsigned long l__,h__; \
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rdmsr (msr, l__, h__); \
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val = l__; \
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val |= ((u64)h__<<32); \
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} while(0)
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static inline void wrmsrl (unsigned long msr, unsigned long long val)
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{
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unsigned long lo, hi;
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lo = (unsigned long) val;
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hi = val >> 32;
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wrmsr (msr, lo, hi);
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}
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/* wrmsr with exception handling */
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#define wrmsr_safe(msr,a,b) ({ int ret__; \
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asm volatile("2: wrmsr ; xorl %0,%0\n" \
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"1:\n\t" \
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".section .fixup,\"ax\"\n\t" \
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"3: movl %4,%0 ; jmp 1b\n\t" \
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".previous\n\t" \
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".section __ex_table,\"a\"\n" \
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" .align 4\n\t" \
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" .long 2b,3b\n\t" \
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".previous" \
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: "=a" (ret__) \
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: "c" (msr), "0" (a), "d" (b), "i" (-EFAULT));\
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ret__; })
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/* rdmsr with exception handling */
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#define rdmsr_safe(msr,a,b) ({ int ret__; \
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asm volatile("2: rdmsr ; xorl %0,%0\n" \
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"1:\n\t" \
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".section .fixup,\"ax\"\n\t" \
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"3: movl %4,%0 ; jmp 1b\n\t" \
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".previous\n\t" \
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".section __ex_table,\"a\"\n" \
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" .align 4\n\t" \
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" .long 2b,3b\n\t" \
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".previous" \
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: "=r" (ret__), "=a" (*(a)), "=d" (*(b)) \
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: "c" (msr), "i" (-EFAULT));\
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ret__; })
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#define rdtsc(low,high) \
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__asm__ __volatile__("rdtsc" : "=a" (low), "=d" (high))
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#define rdtscl(low) \
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__asm__ __volatile__("rdtsc" : "=a" (low) : : "edx")
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#define rdtscll(val) \
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__asm__ __volatile__("rdtsc" : "=A" (val))
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#define write_tsc(val1,val2) wrmsr(0x10, val1, val2)
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#define rdpmc(counter,low,high) \
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__asm__ __volatile__("rdpmc" \
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: "=a" (low), "=d" (high) \
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: "c" (counter))
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#endif /* !CONFIG_PARAVIRT */
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/* symbolic names for some interesting MSRs */
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/* Intel defined MSRs. */
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#define MSR_IA32_P5_MC_ADDR 0
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#define MSR_IA32_P5_MC_TYPE 1
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#define MSR_IA32_PLATFORM_ID 0x17
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#define MSR_IA32_EBL_CR_POWERON 0x2a
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#define MSR_IA32_APICBASE 0x1b
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#define MSR_IA32_APICBASE_BSP (1<<8)
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#define MSR_IA32_APICBASE_ENABLE (1<<11)
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#define MSR_IA32_APICBASE_BASE (0xfffff<<12)
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#define MSR_IA32_UCODE_WRITE 0x79
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#define MSR_IA32_UCODE_REV 0x8b
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#define MSR_P6_PERFCTR0 0xc1
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#define MSR_P6_PERFCTR1 0xc2
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#define MSR_FSB_FREQ 0xcd
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#define MSR_IA32_BBL_CR_CTL 0x119
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#define MSR_IA32_SYSENTER_CS 0x174
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#define MSR_IA32_SYSENTER_ESP 0x175
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#define MSR_IA32_SYSENTER_EIP 0x176
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#define MSR_IA32_MCG_CAP 0x179
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#define MSR_IA32_MCG_STATUS 0x17a
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#define MSR_IA32_MCG_CTL 0x17b
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/* P4/Xeon+ specific */
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#define MSR_IA32_MCG_EAX 0x180
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#define MSR_IA32_MCG_EBX 0x181
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#define MSR_IA32_MCG_ECX 0x182
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#define MSR_IA32_MCG_EDX 0x183
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#define MSR_IA32_MCG_ESI 0x184
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#define MSR_IA32_MCG_EDI 0x185
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#define MSR_IA32_MCG_EBP 0x186
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#define MSR_IA32_MCG_ESP 0x187
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#define MSR_IA32_MCG_EFLAGS 0x188
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#define MSR_IA32_MCG_EIP 0x189
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#define MSR_IA32_MCG_RESERVED 0x18A
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#define MSR_P6_EVNTSEL0 0x186
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#define MSR_P6_EVNTSEL1 0x187
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#define MSR_IA32_PERF_STATUS 0x198
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#define MSR_IA32_PERF_CTL 0x199
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#define MSR_IA32_MPERF 0xE7
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#define MSR_IA32_APERF 0xE8
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#define MSR_IA32_THERM_CONTROL 0x19a
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#define MSR_IA32_THERM_INTERRUPT 0x19b
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#define MSR_IA32_THERM_STATUS 0x19c
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#define MSR_IA32_MISC_ENABLE 0x1a0
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#define MSR_IA32_DEBUGCTLMSR 0x1d9
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#define MSR_IA32_LASTBRANCHFROMIP 0x1db
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#define MSR_IA32_LASTBRANCHTOIP 0x1dc
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#define MSR_IA32_LASTINTFROMIP 0x1dd
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#define MSR_IA32_LASTINTTOIP 0x1de
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#define MSR_IA32_MC0_CTL 0x400
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#define MSR_IA32_MC0_STATUS 0x401
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#define MSR_IA32_MC0_ADDR 0x402
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#define MSR_IA32_MC0_MISC 0x403
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#define MSR_IA32_PEBS_ENABLE 0x3f1
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#define MSR_IA32_DS_AREA 0x600
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#define MSR_IA32_PERF_CAPABILITIES 0x345
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/* Pentium IV performance counter MSRs */
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#define MSR_P4_BPU_PERFCTR0 0x300
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#define MSR_P4_BPU_PERFCTR1 0x301
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#define MSR_P4_BPU_PERFCTR2 0x302
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#define MSR_P4_BPU_PERFCTR3 0x303
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#define MSR_P4_MS_PERFCTR0 0x304
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#define MSR_P4_MS_PERFCTR1 0x305
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#define MSR_P4_MS_PERFCTR2 0x306
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#define MSR_P4_MS_PERFCTR3 0x307
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#define MSR_P4_FLAME_PERFCTR0 0x308
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#define MSR_P4_FLAME_PERFCTR1 0x309
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#define MSR_P4_FLAME_PERFCTR2 0x30a
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#define MSR_P4_FLAME_PERFCTR3 0x30b
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#define MSR_P4_IQ_PERFCTR0 0x30c
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#define MSR_P4_IQ_PERFCTR1 0x30d
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#define MSR_P4_IQ_PERFCTR2 0x30e
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#define MSR_P4_IQ_PERFCTR3 0x30f
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#define MSR_P4_IQ_PERFCTR4 0x310
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#define MSR_P4_IQ_PERFCTR5 0x311
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#define MSR_P4_BPU_CCCR0 0x360
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#define MSR_P4_BPU_CCCR1 0x361
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#define MSR_P4_BPU_CCCR2 0x362
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#define MSR_P4_BPU_CCCR3 0x363
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#define MSR_P4_MS_CCCR0 0x364
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#define MSR_P4_MS_CCCR1 0x365
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#define MSR_P4_MS_CCCR2 0x366
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#define MSR_P4_MS_CCCR3 0x367
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#define MSR_P4_FLAME_CCCR0 0x368
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#define MSR_P4_FLAME_CCCR1 0x369
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#define MSR_P4_FLAME_CCCR2 0x36a
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#define MSR_P4_FLAME_CCCR3 0x36b
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#define MSR_P4_IQ_CCCR0 0x36c
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#define MSR_P4_IQ_CCCR1 0x36d
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#define MSR_P4_IQ_CCCR2 0x36e
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#define MSR_P4_IQ_CCCR3 0x36f
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#define MSR_P4_IQ_CCCR4 0x370
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#define MSR_P4_IQ_CCCR5 0x371
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#define MSR_P4_ALF_ESCR0 0x3ca
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#define MSR_P4_ALF_ESCR1 0x3cb
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#define MSR_P4_BPU_ESCR0 0x3b2
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#define MSR_P4_BPU_ESCR1 0x3b3
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#define MSR_P4_BSU_ESCR0 0x3a0
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#define MSR_P4_BSU_ESCR1 0x3a1
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#define MSR_P4_CRU_ESCR0 0x3b8
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#define MSR_P4_CRU_ESCR1 0x3b9
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#define MSR_P4_CRU_ESCR2 0x3cc
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#define MSR_P4_CRU_ESCR3 0x3cd
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#define MSR_P4_CRU_ESCR4 0x3e0
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#define MSR_P4_CRU_ESCR5 0x3e1
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#define MSR_P4_DAC_ESCR0 0x3a8
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#define MSR_P4_DAC_ESCR1 0x3a9
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#define MSR_P4_FIRM_ESCR0 0x3a4
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#define MSR_P4_FIRM_ESCR1 0x3a5
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#define MSR_P4_FLAME_ESCR0 0x3a6
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#define MSR_P4_FLAME_ESCR1 0x3a7
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#define MSR_P4_FSB_ESCR0 0x3a2
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#define MSR_P4_FSB_ESCR1 0x3a3
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#define MSR_P4_IQ_ESCR0 0x3ba
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#define MSR_P4_IQ_ESCR1 0x3bb
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#define MSR_P4_IS_ESCR0 0x3b4
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#define MSR_P4_IS_ESCR1 0x3b5
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#define MSR_P4_ITLB_ESCR0 0x3b6
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#define MSR_P4_ITLB_ESCR1 0x3b7
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#define MSR_P4_IX_ESCR0 0x3c8
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#define MSR_P4_IX_ESCR1 0x3c9
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#define MSR_P4_MOB_ESCR0 0x3aa
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#define MSR_P4_MOB_ESCR1 0x3ab
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#define MSR_P4_MS_ESCR0 0x3c0
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#define MSR_P4_MS_ESCR1 0x3c1
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#define MSR_P4_PMH_ESCR0 0x3ac
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#define MSR_P4_PMH_ESCR1 0x3ad
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#define MSR_P4_RAT_ESCR0 0x3bc
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#define MSR_P4_RAT_ESCR1 0x3bd
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#define MSR_P4_SAAT_ESCR0 0x3ae
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#define MSR_P4_SAAT_ESCR1 0x3af
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#define MSR_P4_SSU_ESCR0 0x3be
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#define MSR_P4_SSU_ESCR1 0x3bf /* guess: not defined in manual */
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#define MSR_P4_TBPU_ESCR0 0x3c2
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#define MSR_P4_TBPU_ESCR1 0x3c3
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#define MSR_P4_TC_ESCR0 0x3c4
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#define MSR_P4_TC_ESCR1 0x3c5
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#define MSR_P4_U2L_ESCR0 0x3b0
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#define MSR_P4_U2L_ESCR1 0x3b1
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/* AMD Defined MSRs */
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#define MSR_K6_EFER 0xC0000080
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#define MSR_K6_STAR 0xC0000081
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#define MSR_K6_WHCR 0xC0000082
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#define MSR_K6_UWCCR 0xC0000085
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#define MSR_K6_EPMR 0xC0000086
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#define MSR_K6_PSOR 0xC0000087
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#define MSR_K6_PFIR 0xC0000088
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#define MSR_K7_EVNTSEL0 0xC0010000
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#define MSR_K7_EVNTSEL1 0xC0010001
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#define MSR_K7_EVNTSEL2 0xC0010002
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#define MSR_K7_EVNTSEL3 0xC0010003
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#define MSR_K7_PERFCTR0 0xC0010004
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#define MSR_K7_PERFCTR1 0xC0010005
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#define MSR_K7_PERFCTR2 0xC0010006
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#define MSR_K7_PERFCTR3 0xC0010007
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#define MSR_K7_HWCR 0xC0010015
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#define MSR_K7_CLK_CTL 0xC001001b
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#define MSR_K7_FID_VID_CTL 0xC0010041
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#define MSR_K7_FID_VID_STATUS 0xC0010042
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/* extended feature register */
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#define MSR_EFER 0xc0000080
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/* EFER bits: */
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/* Execute Disable enable */
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#define _EFER_NX 11
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#define EFER_NX (1<<_EFER_NX)
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/* Centaur-Hauls/IDT defined MSRs. */
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#define MSR_IDT_FCR1 0x107
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#define MSR_IDT_FCR2 0x108
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#define MSR_IDT_FCR3 0x109
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#define MSR_IDT_FCR4 0x10a
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#define MSR_IDT_MCR0 0x110
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#define MSR_IDT_MCR1 0x111
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#define MSR_IDT_MCR2 0x112
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#define MSR_IDT_MCR3 0x113
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#define MSR_IDT_MCR4 0x114
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#define MSR_IDT_MCR5 0x115
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#define MSR_IDT_MCR6 0x116
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#define MSR_IDT_MCR7 0x117
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#define MSR_IDT_MCR_CTRL 0x120
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/* VIA Cyrix defined MSRs*/
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#define MSR_VIA_FCR 0x1107
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#define MSR_VIA_LONGHAUL 0x110a
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#define MSR_VIA_RNG 0x110b
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#define MSR_VIA_BCR2 0x1147
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/* Transmeta defined MSRs */
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#define MSR_TMTA_LONGRUN_CTRL 0x80868010
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#define MSR_TMTA_LONGRUN_FLAGS 0x80868011
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#define MSR_TMTA_LRTI_READOUT 0x80868018
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#define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a
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/* Intel Core-based CPU performance counters */
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#define MSR_CORE_PERF_FIXED_CTR0 0x309
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#define MSR_CORE_PERF_FIXED_CTR1 0x30a
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#define MSR_CORE_PERF_FIXED_CTR2 0x30b
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#define MSR_CORE_PERF_FIXED_CTR_CTRL 0x38d
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#define MSR_CORE_PERF_GLOBAL_STATUS 0x38e
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#define MSR_CORE_PERF_GLOBAL_CTRL 0x38f
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#define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x390
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/* Geode defined MSRs */
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#define MSR_GEODE_BUSCONT_CONF0 0x1900
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#endif /* __ASM_MSR_H */
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