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Vector population count instructions for dwords and qwords are going to be available in future Intel Xeon & Xeon Phi processors. Bit 14 of CPUID[level:0x07, ECX] indicates that the instructions are supported by a processor. The specification can be found in the Intel Software Developer Manual (SDM) and in the Instruction Set Extensions Programming Reference (ISE). Populate the feature bit and clear it when xsave is disabled. Signed-off-by: Piotr Luc <piotr.luc@intel.com> Reviewed-by: Borislav Petkov <bp@suse.de> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: kvm@vger.kernel.org Cc: Radim Krčmář <rkrcmar@redhat.com> Link: http://lkml.kernel.org/r/20170110173403.6010-2-piotr.luc@intel.com Signed-off-by: Thomas Gleixner <tglx@linutronix.de> |
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alpha/include | ||
arc/include/uapi/asm | ||
arm/include | ||
arm64/include | ||
frv/include/uapi/asm | ||
h8300/include | ||
hexagon/include/uapi/asm | ||
ia64/include | ||
m32r/include/uapi/asm | ||
microblaze/include/uapi/asm | ||
mips/include | ||
mn10300/include/uapi/asm | ||
parisc/include/uapi/asm | ||
powerpc/include | ||
s390/include | ||
score/include/uapi/asm | ||
sh/include | ||
sparc/include | ||
tile/include | ||
x86 | ||
xtensa/include |