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Add pll preset maps for Realtek codecs' PLL2 freq conversions. Signed-off-by: derek.fang <derek.fang@realtek.com> Link: https://lore.kernel.org/r/1591938925-1070-2-git-send-email-derek.fang@realtek.com Signed-off-by: Mark Brown <broonie@kernel.org>
254 lines
5.3 KiB
C
254 lines
5.3 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* rl6231.c - RL6231 class device shared support
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*
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* Copyright 2014 Realtek Semiconductor Corp.
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*
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* Author: Oder Chiou <oder_chiou@realtek.com>
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*/
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#include <linux/module.h>
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#include <linux/regmap.h>
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#include <linux/gcd.h>
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#include "rl6231.h"
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/**
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* rl6231_get_pre_div - Return the value of pre divider.
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*
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* @map: map for setting.
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* @reg: register.
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* @sft: shift.
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*
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* Return the value of pre divider from given register value.
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* Return negative error code for unexpected register value.
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*/
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int rl6231_get_pre_div(struct regmap *map, unsigned int reg, int sft)
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{
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int pd, val;
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regmap_read(map, reg, &val);
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val = (val >> sft) & 0x7;
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switch (val) {
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case 0:
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case 1:
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case 2:
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case 3:
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pd = val + 1;
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break;
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case 4:
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pd = 6;
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break;
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case 5:
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pd = 8;
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break;
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case 6:
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pd = 12;
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break;
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case 7:
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pd = 16;
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break;
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default:
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pd = -EINVAL;
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break;
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}
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return pd;
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}
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EXPORT_SYMBOL_GPL(rl6231_get_pre_div);
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/**
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* rl6231_calc_dmic_clk - Calculate the frequency divider parameter of dmic.
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*
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* @rate: base clock rate.
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*
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* Choose divider parameter that gives the highest possible DMIC frequency in
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* 1MHz - 3MHz range.
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*/
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int rl6231_calc_dmic_clk(int rate)
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{
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static const int div[] = {2, 3, 4, 6, 8, 12};
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int i;
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if (rate < 1000000 * div[0]) {
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pr_warn("Base clock rate %d is too low\n", rate);
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return -EINVAL;
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}
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for (i = 0; i < ARRAY_SIZE(div); i++) {
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if ((div[i] % 3) == 0)
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continue;
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/* find divider that gives DMIC frequency below 1.536MHz */
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if (1536000 * div[i] >= rate)
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return i;
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}
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pr_warn("Base clock rate %d is too high\n", rate);
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return -EINVAL;
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}
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EXPORT_SYMBOL_GPL(rl6231_calc_dmic_clk);
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struct pll_calc_map {
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unsigned int pll_in;
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unsigned int pll_out;
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int k;
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int n;
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int m;
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bool m_bp;
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bool k_bp;
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};
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static const struct pll_calc_map pll_preset_table[] = {
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{19200000, 4096000, 23, 14, 1, false, false},
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{19200000, 24576000, 3, 30, 3, false, false},
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{48000000, 3840000, 23, 2, 0, false, false},
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{3840000, 24576000, 3, 30, 0, true, false},
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{3840000, 22579200, 3, 5, 0, true, false},
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};
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static unsigned int find_best_div(unsigned int in,
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unsigned int max, unsigned int div)
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{
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unsigned int d;
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if (in <= max)
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return 1;
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d = in / max;
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if (in % max)
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d++;
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while (div % d != 0)
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d++;
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return d;
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}
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/**
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* rl6231_pll_calc - Calcualte PLL M/N/K code.
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* @freq_in: external clock provided to codec.
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* @freq_out: target clock which codec works on.
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* @pll_code: Pointer to structure with M, N, K, m_bypass and k_bypass flag.
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*
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* Calcualte M/N/K code to configure PLL for codec.
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*
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* Returns 0 for success or negative error code.
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*/
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int rl6231_pll_calc(const unsigned int freq_in,
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const unsigned int freq_out, struct rl6231_pll_code *pll_code)
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{
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int max_n = RL6231_PLL_N_MAX, max_m = RL6231_PLL_M_MAX;
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int i, k, n_t;
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int k_t, min_k, max_k, n = 0, m = 0, m_t = 0;
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unsigned int red, pll_out, in_t, out_t, div, div_t;
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unsigned int red_t = abs(freq_out - freq_in);
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unsigned int f_in, f_out, f_max;
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bool m_bypass = false, k_bypass = false;
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if (RL6231_PLL_INP_MAX < freq_in || RL6231_PLL_INP_MIN > freq_in)
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return -EINVAL;
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for (i = 0; i < ARRAY_SIZE(pll_preset_table); i++) {
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if (freq_in == pll_preset_table[i].pll_in &&
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freq_out == pll_preset_table[i].pll_out) {
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k = pll_preset_table[i].k;
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m = pll_preset_table[i].m;
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n = pll_preset_table[i].n;
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m_bypass = pll_preset_table[i].m_bp;
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k_bypass = pll_preset_table[i].k_bp;
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pr_debug("Use preset PLL parameter table\n");
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goto code_find;
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}
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}
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min_k = 80000000 / freq_out - 2;
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max_k = 150000000 / freq_out - 2;
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if (max_k > RL6231_PLL_K_MAX)
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max_k = RL6231_PLL_K_MAX;
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if (min_k > RL6231_PLL_K_MAX)
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min_k = max_k = RL6231_PLL_K_MAX;
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div_t = gcd(freq_in, freq_out);
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f_max = 0xffffffff / RL6231_PLL_N_MAX;
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div = find_best_div(freq_in, f_max, div_t);
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f_in = freq_in / div;
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f_out = freq_out / div;
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k = min_k;
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if (min_k < -1)
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min_k = -1;
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for (k_t = min_k; k_t <= max_k; k_t++) {
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for (n_t = 0; n_t <= max_n; n_t++) {
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in_t = f_in * (n_t + 2);
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pll_out = f_out * (k_t + 2);
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if (in_t == pll_out) {
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m_bypass = true;
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n = n_t;
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k = k_t;
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goto code_find;
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}
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out_t = in_t / (k_t + 2);
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red = abs(f_out - out_t);
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if (red < red_t) {
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m_bypass = true;
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n = n_t;
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m = 0;
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k = k_t;
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if (red == 0)
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goto code_find;
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red_t = red;
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}
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for (m_t = 0; m_t <= max_m; m_t++) {
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out_t = in_t / ((m_t + 2) * (k_t + 2));
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red = abs(f_out - out_t);
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if (red < red_t) {
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m_bypass = false;
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n = n_t;
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m = m_t;
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k = k_t;
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if (red == 0)
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goto code_find;
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red_t = red;
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}
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}
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}
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}
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pr_debug("Only get approximation about PLL\n");
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code_find:
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if (k == -1) {
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k_bypass = true;
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k = 0;
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}
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pll_code->m_bp = m_bypass;
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pll_code->k_bp = k_bypass;
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pll_code->m_code = m;
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pll_code->n_code = n;
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pll_code->k_code = k;
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return 0;
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}
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EXPORT_SYMBOL_GPL(rl6231_pll_calc);
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int rl6231_get_clk_info(int sclk, int rate)
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{
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int i;
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static const int pd[] = {1, 2, 3, 4, 6, 8, 12, 16};
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if (sclk <= 0 || rate <= 0)
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return -EINVAL;
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rate = rate << 8;
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for (i = 0; i < ARRAY_SIZE(pd); i++)
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if (sclk == rate * pd[i])
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return i;
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return -EINVAL;
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}
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EXPORT_SYMBOL_GPL(rl6231_get_clk_info);
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MODULE_DESCRIPTION("RL6231 class device shared support");
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MODULE_AUTHOR("Oder Chiou <oder_chiou@realtek.com>");
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MODULE_LICENSE("GPL v2");
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