mirror of
https://mirrors.bfsu.edu.cn/git/linux.git
synced 2025-01-02 03:44:36 +08:00
0be8907359
Add RZ/G2L MTU3a counter driver. This IP supports the following
phase counting modes on MTU1 and MTU2 channels
1) 16-bit phase counting modes on MTU1 and MTU2 channels.
2) 32-bit phase counting mode by cascading MTU1 and MTU2 channels.
This patch adds 3 counter value channels.
count0: 16-bit phase counter value channel on MTU1
count1: 16-bit phase counter value channel on MTU2
count2: 32-bit phase counter value channel by cascading
MTU1 and MTU2 channels.
The external input phase clock pin for the counter value channels
are as follows:
count0: "MTCLKA-MTCLKB"
count1: "MTCLKA-MTCLKB" or "MTCLKC-MTCLKD"
count2: "MTCLKA-MTCLKB" or "MTCLKC-MTCLKD"
Use the sysfs variable "external_input_phase_clock_select" to select the
external input phase clock pin and "cascade_counts_enable" to enable/
disable cascading of channels.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: William Breathitt Gray <william.gray@linaro.org>
Acked-by: William Breathitt Gray <william.gray@linaro.org>
Signed-off-by: Lee Jones <lee@kernel.org>
Link: https://lore.kernel.org/r/20230330111632.169434-5-biju.das.jz@bp.renesas.com
19 lines
644 B
Makefile
19 lines
644 B
Makefile
# SPDX-License-Identifier: GPL-2.0-only
|
|
#
|
|
# Makefile for Counter devices
|
|
#
|
|
|
|
obj-$(CONFIG_COUNTER) += counter.o
|
|
counter-y := counter-core.o counter-sysfs.o counter-chrdev.o
|
|
|
|
obj-$(CONFIG_104_QUAD_8) += 104-quad-8.o
|
|
obj-$(CONFIG_INTERRUPT_CNT) += interrupt-cnt.o
|
|
obj-$(CONFIG_RZ_MTU3_CNT) += rz-mtu3-cnt.o
|
|
obj-$(CONFIG_STM32_TIMER_CNT) += stm32-timer-cnt.o
|
|
obj-$(CONFIG_STM32_LPTIMER_CNT) += stm32-lptimer-cnt.o
|
|
obj-$(CONFIG_TI_EQEP) += ti-eqep.o
|
|
obj-$(CONFIG_FTM_QUADDEC) += ftm-quaddec.o
|
|
obj-$(CONFIG_MICROCHIP_TCB_CAPTURE) += microchip-tcb-capture.o
|
|
obj-$(CONFIG_INTEL_QEP) += intel-qep.o
|
|
obj-$(CONFIG_TI_ECAP_CAPTURE) += ti-ecap-capture.o
|