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d70229f704
This adds dpm support for trinity asics. This includes: - clockgating - powergating - dynamic engine clock scaling - dynamic voltage scaling set radeon.dpm=1 to enable it. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
224 lines
11 KiB
C
224 lines
11 KiB
C
/*
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* Copyright 2012 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Alex Deucher
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*/
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#ifndef _TRINITYD_H_
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#define _TRINITYD_H_
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/* pm registers */
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/* cg */
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#define CG_CGTT_LOCAL_0 0x0
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#define CG_CGTT_LOCAL_1 0x1
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/* smc */
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#define SMU_SCLK_DPM_STATE_0_CNTL_0 0x1f000
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# define STATE_VALID(x) ((x) << 0)
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# define STATE_VALID_MASK (0xff << 0)
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# define STATE_VALID_SHIFT 0
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# define CLK_DIVIDER(x) ((x) << 8)
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# define CLK_DIVIDER_MASK (0xff << 8)
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# define CLK_DIVIDER_SHIFT 8
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# define VID(x) ((x) << 16)
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# define VID_MASK (0xff << 16)
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# define VID_SHIFT 16
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# define LVRT(x) ((x) << 24)
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# define LVRT_MASK (0xff << 24)
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# define LVRT_SHIFT 24
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#define SMU_SCLK_DPM_STATE_0_CNTL_1 0x1f004
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# define DS_DIV(x) ((x) << 0)
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# define DS_DIV_MASK (0xff << 0)
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# define DS_DIV_SHIFT 0
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# define DS_SH_DIV(x) ((x) << 8)
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# define DS_SH_DIV_MASK (0xff << 8)
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# define DS_SH_DIV_SHIFT 8
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# define DISPLAY_WM(x) ((x) << 16)
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# define DISPLAY_WM_MASK (0xff << 16)
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# define DISPLAY_WM_SHIFT 16
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# define VCE_WM(x) ((x) << 24)
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# define VCE_WM_MASK (0xff << 24)
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# define VCE_WM_SHIFT 24
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#define SMU_SCLK_DPM_STATE_0_CNTL_3 0x1f00c
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# define GNB_SLOW(x) ((x) << 0)
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# define GNB_SLOW_MASK (0xff << 0)
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# define GNB_SLOW_SHIFT 0
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# define FORCE_NBPS1(x) ((x) << 8)
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# define FORCE_NBPS1_MASK (0xff << 8)
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# define FORCE_NBPS1_SHIFT 8
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#define SMU_SCLK_DPM_STATE_0_AT 0x1f010
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# define AT(x) ((x) << 0)
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# define AT_MASK (0xff << 0)
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# define AT_SHIFT 0
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#define SMU_SCLK_DPM_STATE_0_PG_CNTL 0x1f014
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# define PD_SCLK_DIVIDER(x) ((x) << 16)
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# define PD_SCLK_DIVIDER_MASK (0xff << 16)
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# define PD_SCLK_DIVIDER_SHIFT 16
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#define SMU_SCLK_DPM_STATE_1_CNTL_0 0x1f020
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#define SMU_SCLK_DPM_CNTL 0x1f100
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# define SCLK_DPM_EN(x) ((x) << 0)
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# define SCLK_DPM_EN_MASK (0xff << 0)
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# define SCLK_DPM_EN_SHIFT 0
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# define SCLK_DPM_BOOT_STATE(x) ((x) << 16)
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# define SCLK_DPM_BOOT_STATE_MASK (0xff << 16)
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# define SCLK_DPM_BOOT_STATE_SHIFT 16
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# define VOLTAGE_CHG_EN(x) ((x) << 24)
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# define VOLTAGE_CHG_EN_MASK (0xff << 24)
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# define VOLTAGE_CHG_EN_SHIFT 24
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#define SMU_SCLK_DPM_TT_CNTL 0x1f108
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# define SCLK_TT_EN(x) ((x) << 0)
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# define SCLK_TT_EN_MASK (0xff << 0)
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# define SCLK_TT_EN_SHIFT 0
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#define SMU_SCLK_DPM_TTT 0x1f10c
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# define LT(x) ((x) << 0)
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# define LT_MASK (0xffff << 0)
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# define LT_SHIFT 0
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# define HT(x) ((x) << 16)
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# define HT_MASK (0xffff << 16)
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# define HT_SHIFT 16
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#define SMU_S_PG_CNTL 0x1f118
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# define DS_PG_EN(x) ((x) << 16)
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# define DS_PG_EN_MASK (0xff << 16)
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# define DS_PG_EN_SHIFT 16
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#define GFX_POWER_GATING_CNTL 0x1f38c
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# define PDS_DIV(x) ((x) << 0)
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# define PDS_DIV_MASK (0xff << 0)
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# define PDS_DIV_SHIFT 0
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# define SSSD(x) ((x) << 8)
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# define SSSD_MASK (0xff << 8)
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# define SSSD_SHIFT 8
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#define PM_CONFIG 0x1f428
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# define SVI_Mode (1 << 29)
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#define PM_I_CNTL_1 0x1f464
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# define SCLK_DPM(x) ((x) << 0)
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# define SCLK_DPM_MASK (0xff << 0)
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# define SCLK_DPM_SHIFT 0
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# define DS_PG_CNTL(x) ((x) << 16)
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# define DS_PG_CNTL_MASK (0xff << 16)
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# define DS_PG_CNTL_SHIFT 16
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#define PM_TP 0x1f468
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#define NB_PSTATE_CONFIG 0x1f5f8
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# define Dpm0PgNbPsLo(x) ((x) << 0)
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# define Dpm0PgNbPsLo_MASK (3 << 0)
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# define Dpm0PgNbPsLo_SHIFT 0
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# define Dpm0PgNbPsHi(x) ((x) << 2)
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# define Dpm0PgNbPsHi_MASK (3 << 2)
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# define Dpm0PgNbPsHi_SHIFT 2
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# define DpmXNbPsLo(x) ((x) << 4)
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# define DpmXNbPsLo_MASK (3 << 4)
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# define DpmXNbPsLo_SHIFT 4
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# define DpmXNbPsHi(x) ((x) << 6)
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# define DpmXNbPsHi_MASK (3 << 6)
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# define DpmXNbPsHi_SHIFT 6
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#define DC_CAC_VALUE 0x1f908
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#define GPU_CAC_AVRG_CNTL 0x1f920
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# define WINDOW_SIZE(x) ((x) << 0)
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# define WINDOW_SIZE_MASK (0xff << 0)
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# define WINDOW_SIZE_SHIFT 0
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#define CC_SMU_MISC_FUSES 0xe0001004
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# define MinSClkDid(x) ((x) << 2)
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# define MinSClkDid_MASK (0x7f << 2)
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# define MinSClkDid_SHIFT 2
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#define CC_SMU_TST_EFUSE1_MISC 0xe000101c
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# define RB_BACKEND_DISABLE(x) ((x) << 16)
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# define RB_BACKEND_DISABLE_MASK (3 << 16)
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# define RB_BACKEND_DISABLE_SHIFT 16
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#define SMU_SCRATCH_A 0xe0003024
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#define SMU_SCRATCH0 0xe0003040
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/* mmio */
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#define SMC_INT_REQ 0x220
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#define SMC_MESSAGE_0 0x22c
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#define SMC_RESP_0 0x230
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#define GENERAL_PWRMGT 0x670
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# define GLOBAL_PWRMGT_EN (1 << 0)
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#define SCLK_PWRMGT_CNTL 0x678
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# define DYN_PWR_DOWN_EN (1 << 2)
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# define RESET_BUSY_CNT (1 << 4)
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# define RESET_SCLK_CNT (1 << 5)
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# define DYN_GFX_CLK_OFF_EN (1 << 7)
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# define GFX_CLK_FORCE_ON (1 << 8)
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# define DYNAMIC_PM_EN (1 << 21)
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#define TARGET_AND_CURRENT_PROFILE_INDEX 0x684
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# define TARGET_STATE(x) ((x) << 0)
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# define TARGET_STATE_MASK (0xf << 0)
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# define TARGET_STATE_SHIFT 0
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# define CURRENT_STATE(x) ((x) << 4)
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# define CURRENT_STATE_MASK (0xf << 4)
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# define CURRENT_STATE_SHIFT 4
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#define CG_GIPOTS 0x6d8
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# define CG_GIPOT(x) ((x) << 16)
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# define CG_GIPOT_MASK (0xffff << 16)
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# define CG_GIPOT_SHIFT 16
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#define CG_PG_CTRL 0x6e0
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# define SP(x) ((x) << 0)
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# define SP_MASK (0xffff << 0)
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# define SP_SHIFT 0
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# define SU(x) ((x) << 16)
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# define SU_MASK (0xffff << 16)
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# define SU_SHIFT 16
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#define CG_THERMAL_INT_CTRL 0x738
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# define DIG_THERM_INTH(x) ((x) << 0)
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# define DIG_THERM_INTH_MASK (0xff << 0)
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# define DIG_THERM_INTH_SHIFT 0
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# define DIG_THERM_INTL(x) ((x) << 8)
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# define DIG_THERM_INTL_MASK (0xff << 8)
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# define DIG_THERM_INTL_SHIFT 8
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# define THERM_INTH_MASK (1 << 24)
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# define THERM_INTL_MASK (1 << 25)
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#define CG_CG_VOLTAGE_CNTL 0x770
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# define EN (1 << 9)
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#define HW_REV 0x5564
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# define ATI_REV_ID_MASK (0xf << 28)
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# define ATI_REV_ID_SHIFT 28
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/* 0 = A0, 1 = A1, 2 = B0, 3 = C0, etc. */
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#define CGTS_SM_CTRL_REG 0x9150
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#define GB_ADDR_CONFIG 0x98f8
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#endif
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