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There is no public clock tree that implies such dependencies between the MG/MG-core/AXI clocks and the COMPHY IP but accessing the COMPHY registers while one of the three clocks are disabled stalls the CPU. This happens if, for instance, the COMPHY driver probe is deferred (eg. the USB Vbus regulator driver is not yet visible). The MVPP2 driver which also needs these clocks (among others) will prepare/enable the clocks, then be deferred, and disable/unprepare them. Next COMPHY lane to be configured would produce an infinite stall. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Tested-by: Grzegorz Jaszczyk <jaz@semihalf.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> |
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| .. | ||
| Kconfig | ||
| Makefile | ||
| phy-armada38x-comphy.c | ||
| phy-armada375-usb2.c | ||
| phy-berlin-sata.c | ||
| phy-berlin-usb.c | ||
| phy-mvebu-a3700-comphy.c | ||
| phy-mvebu-a3700-utmi.c | ||
| phy-mvebu-cp110-comphy.c | ||
| phy-mvebu-sata.c | ||
| phy-pxa-28nm-hsic.c | ||
| phy-pxa-28nm-usb2.c | ||
| phy-pxa-usb.c | ||