Palmer Dabbelt 0619ff9f02 Merge patch series "Add support to handle misaligned accesses in S-mode" ... Clément Léger <cleger@rivosinc.com> says: Since commit 61cadb9 ("Provide new description of misaligned load/store behavior compatible with privileged architecture.") in the RISC-V ISA manual, it is stated that misaligned load/store might not be supported. However, the RISC-V kernel uABI describes that misaligned accesses are supported. In order to support that, this series adds support for S-mode handling of misaligned accesses as well support for prctl(PR_UNALIGN). Handling misaligned access in kernel allows for a finer grain control of the misaligned accesses behavior, and thanks to the prctl() call, can allow disabling misaligned access emulation to generate SIGBUS. User space can then optimize its software by removing such access based on SIGBUS generation. This series is useful when using a SBI implementation that does not handle misaligned traps as well as detecting misaligned accesses generated by userspace application using the prctrl(PR_SET_UNALIGN) feature. This series can be tested using the spike simulator[1] and a modified openSBI version[2] which allows to always delegate misaligned load/store to S-mode. A test[3] that exercise various instructions/registers can be executed to verify the unaligned access support. [1] https://github.com/riscv-software-src/riscv-isa-sim [2] https://github.com/rivosinc/opensbi/tree/dev/cleger/no_misaligned [3] https://github.com/clementleger/unaligned_test * b4-shazam-merge: riscv: add support for PR_SET_UNALIGN and PR_GET_UNALIGN riscv: report misaligned accesses emulation to hwprobe riscv: annotate check_unaligned_access_boot_cpu() with __init riscv: add support for sysctl unaligned_enabled control riscv: add floating point insn support to misaligned access emulation riscv: report perf event for misaligned fault riscv: add support for misaligned trap handling in S-mode riscv: remove unused functions in traps_misaligned.c Link: https://lore.kernel.org/r/20231004151405.521596-1-cleger@rivosinc.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>		2023-11-05 06:42:51 -08:00
..
boot	RISC-V Devicetrees for v6.6 Part 2	2023-08-21 21:47:55 -04:00
configs	riscv: configs: defconfig: Enable configs required for RZ/Five SoC	2023-11-02 14:05:29 -07:00
errata	Merge patch series "Add non-coherent DMA support for AX45MP"	2023-09-08 11:24:34 -07:00
include	Merge patch series "Add support to handle misaligned accesses in S-mode"	2023-11-05 06:42:51 -08:00
kernel	Merge patch series "Add support to handle misaligned accesses in S-mode"	2023-11-05 06:42:51 -08:00
kvm	KVM/riscv changes for 6.6	2023-08-31 13:25:55 -04:00
lib	riscv: uaccess: Return the number of bytes effectively not copied	2023-08-16 07:30:06 -07:00
mm	Merge patch series "RISC-V: ACPI improvements"	2023-10-31 19:15:57 -07:00
net	bpf, riscv: use prog pack allocator in the BPF JIT	2023-09-06 06:26:07 -07:00
purgatory	Merge patch series "riscv: SCS support"	2023-11-02 14:05:23 -07:00
tools	riscv: Check relocations at compile time	2023-04-19 07:46:32 -07:00
Kbuild	kexec: rename ARCH_HAS_KEXEC_PURGATORY	2023-08-18 10:18:54 -07:00
Kconfig	Merge patch series "Add support to handle misaligned accesses in S-mode"	2023-11-05 06:42:51 -08:00
Kconfig.debug	RISC-V: Remove EARLY_PRINTK support	2018-12-17 10:23:46 -08:00
Kconfig.errata	riscv: Kconfig.errata: Add dependency for RISCV_SBI in ERRATA_ANDES config	2023-09-08 11:25:28 -07:00
Kconfig.socs	RISC-V: make ARCH_THEAD preclude XIP_KERNEL	2023-07-05 22:21:23 +02:00
Makefile	riscv: Implement Shadow Call Stack	2023-10-27 14:43:08 -07:00
Makefile.postlink	riscv: Use --emit-relocs in order to move .rela.dyn in init	2023-04-19 07:46:33 -07:00