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The exynos5-dp node needs a clock specified using the common clock framework. Signed-off-by: Jingoo Han <jg1.han@samsung.com> Reviewed-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
87 lines
2.3 KiB
Plaintext
87 lines
2.3 KiB
Plaintext
The Exynos display port interface should be configured based on
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the type of panel connected to it.
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We use two nodes:
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-dp-controller node
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-dptx-phy node(defined inside dp-controller node)
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For the DP-PHY initialization, we use the dptx-phy node.
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Required properties for dptx-phy:
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-reg:
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Base address of DP PHY register.
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-samsung,enable-mask:
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The bit-mask used to enable/disable DP PHY.
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For the Panel initialization, we read data from dp-controller node.
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Required properties for dp-controller:
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-compatible:
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should be "samsung,exynos5-dp".
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-reg:
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physical base address of the controller and length
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of memory mapped region.
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-interrupts:
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interrupt combiner values.
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-clocks:
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from common clock binding: handle to dp clock.
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-clock-names:
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from common clock binding: Shall be "dp".
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-interrupt-parent:
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phandle to Interrupt combiner node.
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-samsung,color-space:
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input video data format.
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COLOR_RGB = 0, COLOR_YCBCR422 = 1, COLOR_YCBCR444 = 2
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-samsung,dynamic-range:
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dynamic range for input video data.
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VESA = 0, CEA = 1
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-samsung,ycbcr-coeff:
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YCbCr co-efficients for input video.
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COLOR_YCBCR601 = 0, COLOR_YCBCR709 = 1
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-samsung,color-depth:
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number of bits per colour component.
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COLOR_6 = 0, COLOR_8 = 1, COLOR_10 = 2, COLOR_12 = 3
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-samsung,link-rate:
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link rate supported by the panel.
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LINK_RATE_1_62GBPS = 0x6, LINK_RATE_2_70GBPS = 0x0A
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-samsung,lane-count:
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number of lanes supported by the panel.
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LANE_COUNT1 = 1, LANE_COUNT2 = 2, LANE_COUNT4 = 4
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Optional properties for dp-controller:
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-interlaced:
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interlace scan mode.
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Progressive if defined, Interlaced if not defined
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-vsync-active-high:
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VSYNC polarity configuration.
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High if defined, Low if not defined
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-hsync-active-high:
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HSYNC polarity configuration.
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High if defined, Low if not defined
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Example:
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SOC specific portion:
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dp-controller {
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compatible = "samsung,exynos5-dp";
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reg = <0x145b0000 0x10000>;
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interrupts = <10 3>;
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interrupt-parent = <&combiner>;
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clocks = <&clock 342>;
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clock-names = "dp";
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dptx-phy {
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reg = <0x10040720>;
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samsung,enable-mask = <1>;
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};
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};
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Board Specific portion:
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dp-controller {
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samsung,color-space = <0>;
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samsung,dynamic-range = <0>;
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samsung,ycbcr-coeff = <0>;
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samsung,color-depth = <1>;
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samsung,link-rate = <0x0a>;
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samsung,lane-count = <4>;
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};
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