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a7bea83089
Some Intel CPUs don't recognize 64-bit XORs as zeroing idioms. Zeroing idioms don't require execution bandwidth, as they're being taken care of in the frontend (through register renaming). Use 32-bit XORs instead. Signed-off-by: Jan Beulich <jbeulich@suse.com> Cc: Alok Kataria <akataria@vmware.com> Cc: Andy Lutomirski <luto@kernel.org> Cc: Borislav Petkov <bp@alien8.de> Cc: Brian Gerst <brgerst@gmail.com> Cc: Denys Vlasenko <dvlasenk@redhat.com> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Josh Poimboeuf <jpoimboe@redhat.com> Cc: Juergen Gross <jgross@suse.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: davem@davemloft.net Cc: herbert@gondor.apana.org.au Cc: pavel@ucw.cz Cc: rjw@rjwysocki.net Link: http://lkml.kernel.org/r/5B39FF1A02000078001CFB54@prv1-mh.provo.novell.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
93 lines
2.6 KiB
C
93 lines
2.6 KiB
C
// SPDX-License-Identifier: GPL-2.0
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#include <asm/paravirt.h>
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#include <asm/asm-offsets.h>
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#include <linux/stringify.h>
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DEF_NATIVE(pv_irq_ops, irq_disable, "cli");
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DEF_NATIVE(pv_irq_ops, irq_enable, "sti");
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DEF_NATIVE(pv_irq_ops, restore_fl, "pushq %rdi; popfq");
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DEF_NATIVE(pv_irq_ops, save_fl, "pushfq; popq %rax");
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DEF_NATIVE(pv_mmu_ops, read_cr2, "movq %cr2, %rax");
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DEF_NATIVE(pv_mmu_ops, read_cr3, "movq %cr3, %rax");
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DEF_NATIVE(pv_mmu_ops, write_cr3, "movq %rdi, %cr3");
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DEF_NATIVE(pv_cpu_ops, wbinvd, "wbinvd");
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DEF_NATIVE(pv_cpu_ops, usergs_sysret64, "swapgs; sysretq");
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DEF_NATIVE(pv_cpu_ops, swapgs, "swapgs");
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DEF_NATIVE(, mov32, "mov %edi, %eax");
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DEF_NATIVE(, mov64, "mov %rdi, %rax");
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#if defined(CONFIG_PARAVIRT_SPINLOCKS)
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DEF_NATIVE(pv_lock_ops, queued_spin_unlock, "movb $0, (%rdi)");
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DEF_NATIVE(pv_lock_ops, vcpu_is_preempted, "xor %eax, %eax");
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#endif
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unsigned paravirt_patch_ident_32(void *insnbuf, unsigned len)
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{
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return paravirt_patch_insns(insnbuf, len,
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start__mov32, end__mov32);
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}
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unsigned paravirt_patch_ident_64(void *insnbuf, unsigned len)
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{
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return paravirt_patch_insns(insnbuf, len,
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start__mov64, end__mov64);
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}
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extern bool pv_is_native_spin_unlock(void);
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extern bool pv_is_native_vcpu_is_preempted(void);
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unsigned native_patch(u8 type, u16 clobbers, void *ibuf,
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unsigned long addr, unsigned len)
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{
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const unsigned char *start, *end;
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unsigned ret;
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#define PATCH_SITE(ops, x) \
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case PARAVIRT_PATCH(ops.x): \
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start = start_##ops##_##x; \
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end = end_##ops##_##x; \
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goto patch_site
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switch(type) {
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PATCH_SITE(pv_irq_ops, restore_fl);
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PATCH_SITE(pv_irq_ops, save_fl);
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PATCH_SITE(pv_irq_ops, irq_enable);
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PATCH_SITE(pv_irq_ops, irq_disable);
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PATCH_SITE(pv_cpu_ops, usergs_sysret64);
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PATCH_SITE(pv_cpu_ops, swapgs);
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PATCH_SITE(pv_mmu_ops, read_cr2);
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PATCH_SITE(pv_mmu_ops, read_cr3);
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PATCH_SITE(pv_mmu_ops, write_cr3);
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PATCH_SITE(pv_cpu_ops, wbinvd);
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#if defined(CONFIG_PARAVIRT_SPINLOCKS)
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case PARAVIRT_PATCH(pv_lock_ops.queued_spin_unlock):
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if (pv_is_native_spin_unlock()) {
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start = start_pv_lock_ops_queued_spin_unlock;
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end = end_pv_lock_ops_queued_spin_unlock;
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goto patch_site;
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}
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goto patch_default;
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case PARAVIRT_PATCH(pv_lock_ops.vcpu_is_preempted):
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if (pv_is_native_vcpu_is_preempted()) {
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start = start_pv_lock_ops_vcpu_is_preempted;
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end = end_pv_lock_ops_vcpu_is_preempted;
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goto patch_site;
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}
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goto patch_default;
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#endif
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default:
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patch_default: __maybe_unused
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ret = paravirt_patch_default(type, clobbers, ibuf, addr, len);
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break;
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patch_site:
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ret = paravirt_patch_insns(ibuf, len, start, end);
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break;
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}
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#undef PATCH_SITE
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return ret;
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}
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