Andrzej Hajda 04aa64375f drm/i915: fix TLB invalidation for Gen12 video and compute engines ... In case of Gen12 video and compute engines, TLB_INV registers are masked - to modify one bit, corresponding bit in upper half of the register must be enabled, otherwise nothing happens. CVE: CVE-2022-4139 Suggested-by: Chris Wilson <chris.p.wilson@intel.com> Signed-off-by: Andrzej Hajda <andrzej.hajda@intel.com> Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch> Fixes: 7938d61591 ("drm/i915: Flush TLBs before releasing backing store") Cc: stable@vger.kernel.org Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>		2022-11-30 08:44:00 -08:00
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drm	drm/i915: fix TLB invalidation for Gen12 video and compute engines	2022-11-30 08:44:00 -08:00
host1x	gpu: host1x: Avoid trying to use GART on Tegra20	2022-11-18 09:33:20 +01:00
ipu-v3	drm/imx: various cleanups	2022-05-06 15:07:39 +10:00
trace
vga
Makefile	gpu: host1x: Add context bus	2022-06-01 11:50:42 +02:00