linux/drivers/clk/ingenic
Paul Cercueil 037f1ffd0f clk: ingenic: Remove pll_info.no_bypass_bit
We can express that a PLL has no bypass bit by simply setting the
.bypass_bit field to a negative value.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Link: https://lore.kernel.org/r/20210530164923.18134-5-paul@crapouillou.net
Tested-by: 周琰杰 (Zhou Yanjie)<zhouyanjie@wanyeetech.com> # on CU1830-neo/X1830
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27 19:49:17 -07:00
..
cgu.c clk: ingenic: Remove pll_info.no_bypass_bit 2021-06-27 19:49:17 -07:00
cgu.h clk: ingenic: Remove pll_info.no_bypass_bit 2021-06-27 19:49:17 -07:00
jz4725b-cgu.c clk: Support bypassing dividers 2021-06-27 19:49:17 -07:00
jz4740-cgu.c clk: Support bypassing dividers 2021-06-27 19:49:17 -07:00
jz4770-cgu.c clk: ingenic: Remove pll_info.no_bypass_bit 2021-06-27 19:49:17 -07:00
jz4780-cgu.c clk: JZ4780: Reformat the code to align it. 2020-07-27 18:18:14 -07:00
Kconfig clk: Ingenic: Add CGU driver for X1830. 2020-05-28 16:13:19 -07:00
Makefile clk: Ingenic: Add CGU driver for X1830. 2020-05-28 16:13:19 -07:00
pm.c clk: ingenic: Handle setting the Low-Power Mode bit 2019-06-25 15:43:15 -07:00
pm.h clk: ingenic: Handle setting the Low-Power Mode bit 2019-06-25 15:43:15 -07:00
tcu.c clk: ingenic: Mark ingenic_tcu_of_match as __maybe_unused 2020-05-28 16:47:02 -07:00
x1000-cgu.c clk: X1000: Add support for calculat REFCLK of USB PHY. 2020-07-27 18:18:14 -07:00
x1830-cgu.c clk: Ingenic: Add RTC related clocks for Ingenic SoCs. 2020-07-27 18:17:52 -07:00