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55661fc1f1
This follows the ARM change c01778001a
("ARM: 6379/1: Assume new page cache pages have dirty D-cache") for the
same rationale:
There are places in Linux where writes to newly allocated page
cache pages happen without a subsequent call to flush_dcache_page()
(several PIO drivers including USB HCD). This patch changes the
meaning of PG_arch_1 to be PG_dcache_clean and always flush the
D-cache for a newly mapped page in update_mmu_cache().
This addresses issues seen with executing binaries from MMC, in
addition to some of the other HCDs that don't explicitly do cache
management for their pipe-in buffers.
Requested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
196 lines
4.8 KiB
C
196 lines
4.8 KiB
C
/*
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* arch/sh/mm/cache-sh7705.c
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*
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* Copyright (C) 1999, 2000 Niibe Yutaka
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* Copyright (C) 2004 Alex Song
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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*/
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#include <linux/init.h>
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#include <linux/mman.h>
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#include <linux/mm.h>
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#include <linux/fs.h>
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#include <linux/threads.h>
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#include <asm/addrspace.h>
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#include <asm/page.h>
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#include <asm/pgtable.h>
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#include <asm/processor.h>
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#include <asm/cache.h>
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#include <asm/io.h>
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#include <asm/uaccess.h>
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#include <asm/pgalloc.h>
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#include <asm/mmu_context.h>
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#include <asm/cacheflush.h>
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/*
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* The 32KB cache on the SH7705 suffers from the same synonym problem
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* as SH4 CPUs
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*/
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static inline void cache_wback_all(void)
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{
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unsigned long ways, waysize, addrstart;
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ways = current_cpu_data.dcache.ways;
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waysize = current_cpu_data.dcache.sets;
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waysize <<= current_cpu_data.dcache.entry_shift;
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addrstart = CACHE_OC_ADDRESS_ARRAY;
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do {
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unsigned long addr;
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for (addr = addrstart;
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addr < addrstart + waysize;
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addr += current_cpu_data.dcache.linesz) {
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unsigned long data;
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int v = SH_CACHE_UPDATED | SH_CACHE_VALID;
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data = __raw_readl(addr);
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if ((data & v) == v)
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__raw_writel(data & ~v, addr);
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}
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addrstart += current_cpu_data.dcache.way_incr;
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} while (--ways);
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}
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/*
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* Write back the range of D-cache, and purge the I-cache.
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*
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* Called from kernel/module.c:sys_init_module and routine for a.out format.
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*/
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static void sh7705_flush_icache_range(void *args)
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{
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struct flusher_data *data = args;
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unsigned long start, end;
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start = data->addr1;
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end = data->addr2;
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__flush_wback_region((void *)start, end - start);
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}
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/*
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* Writeback&Invalidate the D-cache of the page
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*/
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static void __flush_dcache_page(unsigned long phys)
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{
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unsigned long ways, waysize, addrstart;
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unsigned long flags;
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phys |= SH_CACHE_VALID;
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/*
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* Here, phys is the physical address of the page. We check all the
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* tags in the cache for those with the same page number as this page
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* (by masking off the lowest 2 bits of the 19-bit tag; these bits are
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* derived from the offset within in the 4k page). Matching valid
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* entries are invalidated.
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*
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* Since 2 bits of the cache index are derived from the virtual page
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* number, knowing this would reduce the number of cache entries to be
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* searched by a factor of 4. However this function exists to deal with
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* potential cache aliasing, therefore the optimisation is probably not
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* possible.
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*/
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local_irq_save(flags);
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jump_to_uncached();
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ways = current_cpu_data.dcache.ways;
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waysize = current_cpu_data.dcache.sets;
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waysize <<= current_cpu_data.dcache.entry_shift;
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addrstart = CACHE_OC_ADDRESS_ARRAY;
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do {
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unsigned long addr;
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for (addr = addrstart;
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addr < addrstart + waysize;
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addr += current_cpu_data.dcache.linesz) {
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unsigned long data;
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data = __raw_readl(addr) & (0x1ffffC00 | SH_CACHE_VALID);
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if (data == phys) {
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data &= ~(SH_CACHE_VALID | SH_CACHE_UPDATED);
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__raw_writel(data, addr);
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}
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}
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addrstart += current_cpu_data.dcache.way_incr;
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} while (--ways);
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back_to_cached();
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local_irq_restore(flags);
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}
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/*
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* Write back & invalidate the D-cache of the page.
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* (To avoid "alias" issues)
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*/
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static void sh7705_flush_dcache_page(void *arg)
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{
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struct page *page = arg;
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struct address_space *mapping = page_mapping(page);
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if (mapping && !mapping_mapped(mapping))
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clear_bit(PG_dcache_clean, &page->flags);
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else
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__flush_dcache_page(__pa(page_address(page)));
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}
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static void sh7705_flush_cache_all(void *args)
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{
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unsigned long flags;
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local_irq_save(flags);
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jump_to_uncached();
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cache_wback_all();
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back_to_cached();
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local_irq_restore(flags);
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}
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/*
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* Write back and invalidate I/D-caches for the page.
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*
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* ADDRESS: Virtual Address (U0 address)
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*/
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static void sh7705_flush_cache_page(void *args)
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{
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struct flusher_data *data = args;
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unsigned long pfn = data->addr2;
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__flush_dcache_page(pfn << PAGE_SHIFT);
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}
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/*
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* This is called when a page-cache page is about to be mapped into a
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* user process' address space. It offers an opportunity for a
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* port to ensure d-cache/i-cache coherency if necessary.
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*
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* Not entirely sure why this is necessary on SH3 with 32K cache but
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* without it we get occasional "Memory fault" when loading a program.
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*/
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static void sh7705_flush_icache_page(void *page)
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{
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__flush_purge_region(page_address(page), PAGE_SIZE);
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}
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void __init sh7705_cache_init(void)
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{
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local_flush_icache_range = sh7705_flush_icache_range;
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local_flush_dcache_page = sh7705_flush_dcache_page;
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local_flush_cache_all = sh7705_flush_cache_all;
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local_flush_cache_mm = sh7705_flush_cache_all;
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local_flush_cache_dup_mm = sh7705_flush_cache_all;
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local_flush_cache_range = sh7705_flush_cache_all;
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local_flush_cache_page = sh7705_flush_cache_page;
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local_flush_icache_page = sh7705_flush_icache_page;
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}
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