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02f513a097
The DDRSDR controller fails miserably to put LPDDR1 memories in self-refresh. Force the controller to think it has DDR2 memories during the self-refresh period, as the DDR2 self-refresh spec is equivalent to LPDDR1, and is correctly implemented in the controller. Assume that the second controller has the same fault, but that is untested. Signed-off-by: Peter Rosin <peda@axentia.se> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> |
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.. | ||
include/mach | ||
at91rm9200_time.c | ||
at91rm9200.c | ||
at91sam9.c | ||
generic.h | ||
Kconfig | ||
Makefile | ||
Makefile.boot | ||
pm_slowclock.S | ||
pm.c | ||
pm.h | ||
sam9_smc.c | ||
sam9_smc.h | ||
sama5.c | ||
setup.c |