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02a841d434
Future work will be headed in the way of separating the policy supplied by the nouveau drm module from the mechanisms provided by the driver core. There will be a couple of major classes (subdev, engine) of driver modules that have clearly defined tasks, and the further directory structure change is to reflect this. No code changes here whatsoever, aside from fixing up a couple of include file pathnames. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
178 lines
4.9 KiB
C
178 lines
4.9 KiB
C
/*
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* Copyright 2012 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#include "drmP.h"
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#include "nouveau_drv.h"
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#include "nouveau_dma.h"
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#include <engine/fifo.h>
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#include <core/ramht.h>
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#include "nouveau_fence.h"
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struct nv84_fence_chan {
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struct nouveau_fence_chan base;
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};
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struct nv84_fence_priv {
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struct nouveau_fence_priv base;
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struct nouveau_gpuobj *mem;
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};
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static int
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nv84_fence_emit(struct nouveau_fence *fence)
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{
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struct nouveau_channel *chan = fence->channel;
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int ret = RING_SPACE(chan, 7);
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if (ret == 0) {
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BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1);
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OUT_RING (chan, NvSema);
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BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
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OUT_RING (chan, upper_32_bits(chan->id * 16));
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OUT_RING (chan, lower_32_bits(chan->id * 16));
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OUT_RING (chan, fence->sequence);
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OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG);
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FIRE_RING (chan);
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}
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return ret;
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}
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static int
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nv84_fence_sync(struct nouveau_fence *fence,
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struct nouveau_channel *prev, struct nouveau_channel *chan)
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{
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int ret = RING_SPACE(chan, 7);
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if (ret == 0) {
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BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1);
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OUT_RING (chan, NvSema);
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BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
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OUT_RING (chan, upper_32_bits(prev->id * 16));
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OUT_RING (chan, lower_32_bits(prev->id * 16));
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OUT_RING (chan, fence->sequence);
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OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_GEQUAL);
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FIRE_RING (chan);
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}
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return ret;
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}
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static u32
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nv84_fence_read(struct nouveau_channel *chan)
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{
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struct nv84_fence_priv *priv = nv_engine(chan->dev, NVOBJ_ENGINE_FENCE);
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return nv_ro32(priv->mem, chan->id * 16);
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}
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static void
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nv84_fence_context_del(struct nouveau_channel *chan, int engine)
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{
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struct nv84_fence_chan *fctx = chan->engctx[engine];
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nouveau_fence_context_del(&fctx->base);
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chan->engctx[engine] = NULL;
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kfree(fctx);
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}
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static int
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nv84_fence_context_new(struct nouveau_channel *chan, int engine)
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{
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struct nv84_fence_priv *priv = nv_engine(chan->dev, engine);
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struct nv84_fence_chan *fctx;
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struct nouveau_gpuobj *obj;
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int ret;
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fctx = chan->engctx[engine] = kzalloc(sizeof(*fctx), GFP_KERNEL);
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if (!fctx)
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return -ENOMEM;
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nouveau_fence_context_new(&fctx->base);
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ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_FROM_MEMORY,
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priv->mem->vinst, priv->mem->size,
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NV_MEM_ACCESS_RW,
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NV_MEM_TARGET_VRAM, &obj);
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if (ret == 0) {
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ret = nouveau_ramht_insert(chan, NvSema, obj);
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nouveau_gpuobj_ref(NULL, &obj);
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nv_wo32(priv->mem, chan->id * 16, 0x00000000);
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}
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if (ret)
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nv84_fence_context_del(chan, engine);
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return ret;
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}
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static int
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nv84_fence_fini(struct drm_device *dev, int engine, bool suspend)
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{
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return 0;
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}
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static int
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nv84_fence_init(struct drm_device *dev, int engine)
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{
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return 0;
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}
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static void
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nv84_fence_destroy(struct drm_device *dev, int engine)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nv84_fence_priv *priv = nv_engine(dev, engine);
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nouveau_gpuobj_ref(NULL, &priv->mem);
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dev_priv->eng[engine] = NULL;
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kfree(priv);
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}
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int
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nv84_fence_create(struct drm_device *dev)
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{
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struct nouveau_fifo_priv *pfifo = nv_engine(dev, NVOBJ_ENGINE_FIFO);
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nv84_fence_priv *priv;
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int ret;
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priv = kzalloc(sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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priv->base.engine.destroy = nv84_fence_destroy;
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priv->base.engine.init = nv84_fence_init;
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priv->base.engine.fini = nv84_fence_fini;
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priv->base.engine.context_new = nv84_fence_context_new;
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priv->base.engine.context_del = nv84_fence_context_del;
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priv->base.emit = nv84_fence_emit;
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priv->base.sync = nv84_fence_sync;
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priv->base.read = nv84_fence_read;
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dev_priv->eng[NVOBJ_ENGINE_FENCE] = &priv->base.engine;
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ret = nouveau_gpuobj_new(dev, NULL, 16 * pfifo->channels,
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0x1000, 0, &priv->mem);
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if (ret)
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goto out;
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out:
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if (ret)
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nv84_fence_destroy(dev, NVOBJ_ENGINE_FENCE);
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return ret;
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}
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